
Christopher Anthony Daley
Examiner (ID: 15564, Phone: (571)272-3625 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2185, 2184, 2111 |
| Total Applications | 1104 |
| Issued Applications | 875 |
| Pending Applications | 67 |
| Abandoned Applications | 176 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20009443
[patent_doc_number] => 20250147665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR ACCESSING MEMORY WITH DIE-TO-DIE INTERFACES
[patent_app_type] => utility
[patent_app_number] => 18/935341
[patent_app_country] => US
[patent_app_date] => 2024-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12544
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935341
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/935341 | SYSTEMS, METHODS, AND APPARATUS FOR ACCESSING MEMORY WITH DIE-TO-DIE INTERFACES | Oct 31, 2024 | Pending |
Array
(
[id] => 20043314
[patent_doc_number] => 20250181536
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => CHIPLET WITH ADDRESS REMAPPER BLOCK
[patent_app_type] => utility
[patent_app_number] => 18/935126
[patent_app_country] => US
[patent_app_date] => 2024-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6531
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935126
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/935126 | Chiplet with address remapper block | Oct 31, 2024 | Issued |
Array
(
[id] => 20883630
[patent_doc_number] => 12699673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-04
[patent_title] => Multi-processor device with external interface failover
[patent_app_type] => utility
[patent_app_number] => 18/919053
[patent_app_country] => US
[patent_app_date] => 2024-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919053
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/919053 | MULTI-PROCESSOR DEVICE WITH EXTERNAL INTERFACE FAILOVER | Oct 16, 2024 | Pending |
Array
(
[id] => 19748018
[patent_doc_number] => 20250036583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/917560
[patent_app_country] => US
[patent_app_date] => 2024-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12544
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917560
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/917560 | MEMORY SYSTEM | Oct 15, 2024 | Pending |
Array
(
[id] => 20666552
[patent_doc_number] => 12608327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-21
[patent_title] => System-on-chip and an interconnect bus included in the system on chip
[patent_app_type] => utility
[patent_app_number] => 18/915833
[patent_app_country] => US
[patent_app_date] => 2024-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6937
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915833
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/915833 | System-on-chip and an interconnect bus included in the system on chip | Oct 14, 2024 | Issued |
Array
(
[id] => 20680603
[patent_doc_number] => 20260119424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-30
[patent_title] => METHOD AND APPARATUS FOR DMA BETWEEN ACCELERATOR CARDS, AND ACCELERATOR CARD, ACCELERATION PLATFORM AND MEDIUM
[patent_app_type] => utility
[patent_app_number] => 19/139813
[patent_app_country] => US
[patent_app_date] => 2024-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10293
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19139813
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/139813 | Method and apparatus for dma between accelerator cards, and accelerator card, acceleration platform and medium | Sep 28, 2024 | Issued |
Array
(
[id] => 20994756
[patent_doc_number] => 12743391
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-09-22
[patent_title] => Programmable logic device system of baseboard, and application device thereof
[patent_app_type] => utility
[patent_app_number] => 19/470727
[patent_app_country] => US
[patent_app_date] => 2024-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5259
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19470727
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/470727 | PROGRAMMABLE LOGIC DEVICE SYSTEM OF BASEBOARD, AND APPLICATION DEVICE THEREOF | Sep 26, 2024 | Pending |
Array
(
[id] => 19819252
[patent_doc_number] => 20250077459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => STACKED DEVICE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/892110
[patent_app_country] => US
[patent_app_date] => 2024-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6931
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18892110
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/892110 | Stacked device system | Sep 19, 2024 | Issued |
Array
(
[id] => 20994751
[patent_doc_number] => 12743386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-09-22
[patent_title] => Memory device including command-address management circuit, method of operating the same, and memory system
[patent_app_type] => utility
[patent_app_number] => 18/829635
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4591
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829635
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/829635 | MEMORY DEVICE INCLUDING COMMAND-ADDRESS MANAGEMENT CIRCUIT, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM | Sep 9, 2024 | Pending |
Array
(
[id] => 19686417
[patent_doc_number] => 20250004962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING
[patent_app_type] => utility
[patent_app_number] => 18/829713
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9390
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829713
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/829713 | DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING | Sep 9, 2024 | Pending |
Array
(
[id] => 20790200
[patent_doc_number] => 12664115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-23
[patent_title] => Sensor data offload
[patent_app_type] => utility
[patent_app_number] => 18/826037
[patent_app_country] => US
[patent_app_date] => 2024-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4579
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826037
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/826037 | Sensor data offload | Sep 4, 2024 | Issued |
Array
(
[id] => 20609999
[patent_doc_number] => 12585601
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Event driven high speed interface counter polling
[patent_app_type] => utility
[patent_app_number] => 18/817511
[patent_app_country] => US
[patent_app_date] => 2024-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11282
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817511
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/817511 | Event driven high speed interface counter polling | Aug 27, 2024 | Issued |
Array
(
[id] => 19635583
[patent_doc_number] => 20240414032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => EQUALIZATION TRAINING METHOD AND APPARATUS, AND SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/810900
[patent_app_country] => US
[patent_app_date] => 2024-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22077
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810900
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/810900 | EQUALIZATION TRAINING METHOD AND APPARATUS, AND SYSTEM | Aug 20, 2024 | Pending |
Array
(
[id] => 19633263
[patent_doc_number] => 20240411712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => METHOD OF CONTROLLING DATA PROCESSING SYSTEM AND DATA PROCESSING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/808703
[patent_app_country] => US
[patent_app_date] => 2024-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808703
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/808703 | METHOD OF CONTROLLING DATA PROCESSING SYSTEM AND DATA PROCESSING SYSTEM | Aug 18, 2024 | Pending |
Array
(
[id] => 19602953
[patent_doc_number] => 20240393833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => NETWORK-CAPABLE DOCKING STATION
[patent_app_type] => utility
[patent_app_number] => 18/791837
[patent_app_country] => US
[patent_app_date] => 2024-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6662
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791837
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/791837 | NETWORK-CAPABLE DOCKING STATION | Jul 31, 2024 | Issued |
Array
(
[id] => 20454789
[patent_doc_number] => 12517843
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-06
[patent_title] => Third party applications for a network-capable docking station
[patent_app_type] => utility
[patent_app_number] => 18/786104
[patent_app_country] => US
[patent_app_date] => 2024-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7188
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786104
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/786104 | Third party applications for a network-capable docking station | Jul 25, 2024 | Issued |
Array
(
[id] => 20635794
[patent_doc_number] => 12596668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Dual interface high-speed memory subsystem
[patent_app_type] => utility
[patent_app_number] => 18/783335
[patent_app_country] => US
[patent_app_date] => 2024-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1132
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783335
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/783335 | Dual interface high-speed memory subsystem | Jul 23, 2024 | Issued |
Array
(
[id] => 19558500
[patent_doc_number] => 20240370292
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => Automatic Reconfiguration of Network Interface Driver on Network Sensor
[patent_app_type] => utility
[patent_app_number] => 18/773734
[patent_app_country] => US
[patent_app_date] => 2024-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773734
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/773734 | Automatic reconfiguration of network interface driver on network sensor host | Jul 15, 2024 | Issued |
Array
(
[id] => 20922674
[patent_doc_number] => 12717735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-25
[patent_title] => Streaming protocol flow control for die-to-die interfaces
[patent_app_type] => utility
[patent_app_number] => 18/765210
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10048
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765210
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/765210 | STREAMING PROTOCOL FLOW CONTROL FOR DIE-TO-DIE INTERFACES | Jul 4, 2024 | Pending |
Array
(
[id] => 19530370
[patent_doc_number] => 20240354272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => END-TO-END ISOLATION OVER PCIE
[patent_app_type] => utility
[patent_app_number] => 18/763195
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8441
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763195
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/763195 | End-to-end isolation over PCIe | Jul 2, 2024 | Issued |