Search

Christopher Anthony Daley

Examiner (ID: 14782, Phone: (571)272-3625 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2111, 2185, 2184
Total Applications
1074
Issued Applications
854
Pending Applications
71
Abandoned Applications
175

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20167439 [patent_doc_number] => 20250259486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => METHOD FOR COMMUNICATION BETWEEN A VEHICLE DIAGNOSTIC NETWORK AND A POWERTRAIN CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/440945 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440945
METHOD FOR COMMUNICATION BETWEEN A VEHICLE DIAGNOSTIC NETWORK AND A POWERTRAIN CONTROLLER Feb 12, 2024 Pending
Array ( [id] => 20167439 [patent_doc_number] => 20250259486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => METHOD FOR COMMUNICATION BETWEEN A VEHICLE DIAGNOSTIC NETWORK AND A POWERTRAIN CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/440945 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440945
METHOD FOR COMMUNICATION BETWEEN A VEHICLE DIAGNOSTIC NETWORK AND A POWERTRAIN CONTROLLER Feb 12, 2024 Pending
Array ( [id] => 20167439 [patent_doc_number] => 20250259486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => METHOD FOR COMMUNICATION BETWEEN A VEHICLE DIAGNOSTIC NETWORK AND A POWERTRAIN CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/440945 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440945
METHOD FOR COMMUNICATION BETWEEN A VEHICLE DIAGNOSTIC NETWORK AND A POWERTRAIN CONTROLLER Feb 12, 2024 Pending
Array ( [id] => 19420013 [patent_doc_number] => 20240296136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => CXL DRAM SWITCH FABRIC [patent_app_type] => utility [patent_app_number] => 18/433191 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433191 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433191
Memory interconnect switch Feb 4, 2024 Issued
Array ( [id] => 20138133 [patent_doc_number] => 20250245177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => USING SYSTEM MEMORY TO STORE INITIALIZATION DATA FOR INITIALIZATION OF DEVICES ON A LINK [patent_app_type] => utility [patent_app_number] => 18/426824 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426824
USING SYSTEM MEMORY TO STORE INITIALIZATION DATA FOR INITIALIZATION OF DEVICES ON A LINK Jan 29, 2024 Pending
Array ( [id] => 20145699 [patent_doc_number] => 12380042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Storage device for outputting interrupt and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/422907 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422907
Storage device for outputting interrupt and method of operating the same Jan 24, 2024 Issued
Array ( [id] => 19174618 [patent_doc_number] => 20240160592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MEMORY DISAGGREGATION AND REALLOCATION [patent_app_type] => utility [patent_app_number] => 18/421506 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421506
Memory disaggregation and reallocation Jan 23, 2024 Issued
Array ( [id] => 19780402 [patent_doc_number] => 12229435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Memory component with input/output data rate alignment [patent_app_type] => utility [patent_app_number] => 18/412731 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412731
Memory component with input/output data rate alignment Jan 14, 2024 Issued
Array ( [id] => 19303359 [patent_doc_number] => 20240231939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => Queueing Storage Operations [patent_app_type] => utility [patent_app_number] => 18/400952 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 54479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400952
Queueing storage operations Dec 28, 2023 Issued
Array ( [id] => 20035078 [patent_doc_number] => 20250173300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SEMICONDUCTOR DEVICES AND COMMUNICATION METHOD BETWEEN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/395758 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395758
Semiconductor devices and communication method between semiconductor devices Dec 25, 2023 Issued
Array ( [id] => 20070805 [patent_doc_number] => 20250209027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => RESILIENT I/O INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/394332 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394332
RESILIENT I/O INTERCONNECT Dec 21, 2023 Pending
Array ( [id] => 20228552 [patent_doc_number] => 12417204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Serial-bus system provided with dynamic address assignment and its method for controlling the same [patent_app_type] => utility [patent_app_number] => 18/541502 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/541502
Serial-bus system provided with dynamic address assignment and its method for controlling the same Dec 14, 2023 Issued
Array ( [id] => 19334428 [patent_doc_number] => 20240248858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SERIAL BUS COMMUNICATION WITHOUT READ INDICATION [patent_app_type] => utility [patent_app_number] => 18/540258 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/540258
Serial bus communication without read indication Dec 13, 2023 Issued
Array ( [id] => 19849012 [patent_doc_number] => 20250094363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => MOBILE DEVICES AND OPERATION METHODS THEREOF, SYSTEMS, AND COMPUTER-READABLE STORAGE MEDIUMS [patent_app_type] => utility [patent_app_number] => 18/535400 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535400
MOBILE DEVICES AND OPERATION METHODS THEREOF, SYSTEMS, AND COMPUTER-READABLE STORAGE MEDIUMS Dec 10, 2023 Pending
Array ( [id] => 20035062 [patent_doc_number] => 20250173284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => CONFIGURING INPUT/OUTPUT (I/O) PORTS IN RESPONSE TO ACCIDENTS [patent_app_type] => utility [patent_app_number] => 18/522667 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522667
CONFIGURING INPUT/OUTPUT (I/O) PORTS IN RESPONSE TO ACCIDENTS Nov 28, 2023 Pending
Array ( [id] => 19055968 [patent_doc_number] => 20240097937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS [patent_app_type] => utility [patent_app_number] => 18/515468 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515468
Signaling of time for communication between integrated circuits using multi-drop bus Nov 20, 2023 Issued
Array ( [id] => 19347518 [patent_doc_number] => 20240256481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Deserializer [patent_app_type] => utility [patent_app_number] => 18/505744 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505744
Deserializer Nov 8, 2023 Issued
Array ( [id] => 20265913 [patent_doc_number] => 12436905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Composable core matrix for service level compliance [patent_app_type] => utility [patent_app_number] => 18/502160 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502160
Composable core matrix for service level compliance Nov 5, 2023 Issued
Array ( [id] => 20265913 [patent_doc_number] => 12436905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Composable core matrix for service level compliance [patent_app_type] => utility [patent_app_number] => 18/502160 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502160
Composable core matrix for service level compliance Nov 5, 2023 Issued
Array ( [id] => 20000809 [patent_doc_number] => 20250139031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DYNAMIC POWER GATING USING DETERMINISTIC INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/498581 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498581 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498581
Dynamic power gating using deterministic interconnect Oct 30, 2023 Issued
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