Search

Christopher B. Shin

Examiner (ID: 8971, Phone: (571)272-4159 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2756, 2182, 2308, 2782, 2317, 2181
Total Applications
1854
Issued Applications
1563
Pending Applications
75
Abandoned Applications
229

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20145682 [patent_doc_number] => 12380025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Storage circuit, chip, data processing method, and electronic device [patent_app_type] => utility [patent_app_number] => 18/633411 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633411 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633411
Storage circuit, chip, data processing method, and electronic device Apr 10, 2024 Issued
Array ( [id] => 19645102 [patent_doc_number] => 20240419622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CONNECTION DEVICE [patent_app_type] => utility [patent_app_number] => 18/612907 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612907
Connection device Mar 20, 2024 Issued
Array ( [id] => 19283951 [patent_doc_number] => 20240220427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC [patent_app_type] => utility [patent_app_number] => 18/605301 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605301
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC Mar 13, 2024 Issued
Array ( [id] => 19220428 [patent_doc_number] => 20240185132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DATA PATH FOR GPU MACHINE LEARNING TRAINING WITH KEY VALUE SSD [patent_app_type] => utility [patent_app_number] => 18/437769 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437769
Data path for GPU machine learning training with key value SSD Feb 8, 2024 Issued
Array ( [id] => 20152225 [patent_doc_number] => 20250252063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SYSTEM AND METHOD FOR DETERMINING PERIPHERAL DEVICE CONFIGURATIONS ACROSS A PLURALITY OF WORKSPACES FOR SEAMLESS USER PERIPHERAL DEVICE WORKSPACE ECOSYSTEM EXPERIENCE [patent_app_type] => utility [patent_app_number] => 18/430712 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430712
System and method for determining peripheral device configurations across a plurality of workspaces for seamless user peripheral device workspace ecosystem experience Feb 1, 2024 Issued
Array ( [id] => 20666557 [patent_doc_number] => 12608332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Systems and methods for direct data transmission in image processing systems [patent_app_type] => utility [patent_app_number] => 18/395486 [patent_app_country] => US [patent_app_date] => 2023-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395486
Systems and methods for direct data transmission in image processing systems Dec 22, 2023 Issued
Array ( [id] => 20595351 [patent_doc_number] => 12579068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Systems, methods, and media for unordered input/output direct memory access operations [patent_app_type] => utility [patent_app_number] => 18/536878 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536878
Systems, methods, and media for unordered input/output direct memory access operations Dec 11, 2023 Issued
Array ( [id] => 20052060 [patent_doc_number] => 20250190282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => Hardware-Assisted Spinlock [patent_app_type] => utility [patent_app_number] => 18/535009 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535009
Hardware-assisted spinlock Dec 10, 2023 Issued
Array ( [id] => 20358875 [patent_doc_number] => 12474870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => System and method for in-SSD data processing engine selection based on stream IDs [patent_app_type] => utility [patent_app_number] => 18/530035 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530035
System and method for in-SSD data processing engine selection based on stream IDs Dec 4, 2023 Issued
Array ( [id] => 20043322 [patent_doc_number] => 20250181544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => METHOD AND DEVICE FOR REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK [patent_app_type] => utility [patent_app_number] => 18/527468 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527468
Method and device for reducing latency in a peripheral component interconnect express link Dec 3, 2023 Issued
Array ( [id] => 19036524 [patent_doc_number] => 20240086339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SYSTEMS, METHODS, AND DEVICES FOR ACCESSING A DEVICE OPERATING SYSTEM OVER AN INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/513490 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513490
Systems, methods, and devices for accessing a device operating system over an interconnect Nov 16, 2023 Issued
Array ( [id] => 19451188 [patent_doc_number] => 20240311318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SYSTEMS AND METHODS FOR A CACHE-COHERENT INTERCONNECT PROTOCOL STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/513496 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513496
Systems and methods for a cache-coherent interconnect protocol storage device Nov 16, 2023 Issued
Array ( [id] => 19021878 [patent_doc_number] => 20240078049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => Analytics, Algorithm Architecture, and Data Processing System and Method [patent_app_type] => utility [patent_app_number] => 18/502275 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502275
Analytics, algorithm architecture, and data processing system and method Nov 5, 2023 Issued
Array ( [id] => 20000801 [patent_doc_number] => 20250139023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => ALLOWING NON-VOLATILE MEMORY EXPRESS (NVMe) OVER FABRIC (NVMe-oF) TRAFFIC OVER INTERFACES USING A SCALABLE END POINT (SEP) ADDRESSING MECHANISM [patent_app_type] => utility [patent_app_number] => 18/498536 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498536
Allowing non-volatile memory express (NVMe) over fabric (NVMe-oF) traffic over interfaces using a scalable end point (SEP) addressing mechanism Oct 30, 2023 Issued
Array ( [id] => 19992738 [patent_doc_number] => 20250130960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Namespace Management Using Mastership In Multi-Host Storage Systems [patent_app_type] => utility [patent_app_number] => 18/493043 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493043
Namespace management using mastership in multi-host storage systems Oct 23, 2023 Issued
Array ( [id] => 19992724 [patent_doc_number] => 20250130946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => MEMORY ADDRESS CACHING FOR NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 18/489260 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489260
Memory address caching for neural networks Oct 17, 2023 Issued
Array ( [id] => 20160145 [patent_doc_number] => 12386774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => AI accelerator apparatus using full mesh connectivity chiplet devices for transformer workloads [patent_app_type] => utility [patent_app_number] => 18/486872 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 56 [patent_no_of_words] => 9101 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/486872
AI accelerator apparatus using full mesh connectivity chiplet devices for transformer workloads Oct 12, 2023 Issued
Array ( [id] => 20454805 [patent_doc_number] => 12517859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Communication device, release method of buffer, and program [patent_app_type] => utility [patent_app_number] => 18/483711 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483711
Communication device, release method of buffer, and program Oct 9, 2023 Issued
Array ( [id] => 20131044 [patent_doc_number] => 12373357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Systems and methods for data communication bus address sharing [patent_app_type] => utility [patent_app_number] => 18/475713 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475713
Systems and methods for data communication bus address sharing Sep 26, 2023 Issued
Array ( [id] => 20117262 [patent_doc_number] => 12366965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Solid state drive with multiplexed internal channel access during program data transfers [patent_app_type] => utility [patent_app_number] => 18/373480 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373480
Solid state drive with multiplexed internal channel access during program data transfers Sep 26, 2023 Issued
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