
Christopher Brown
Examiner (ID: 19398)
| Most Active Art Unit | 1504 |
| Art Unit(s) | 2899, 1504 |
| Total Applications | 247 |
| Issued Applications | 157 |
| Pending Applications | 0 |
| Abandoned Applications | 90 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1390691
[patent_doc_number] => 06552371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-22
[patent_title] => 'Telecommunications switch array with thyristor addressing'
[patent_app_type] => B2
[patent_app_number] => 09/788298
[patent_app_country] => US
[patent_app_date] => 2001-02-16
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/552/06552371.pdf
[firstpage_image] =>[orig_patent_app_number] => 09788298
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/788298 | Telecommunications switch array with thyristor addressing | Feb 15, 2001 | Issued |
Array
(
[id] => 6522512
[patent_doc_number] => 20020109189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-15
[patent_title] => 'Method and structure for providing ESD protection for silicon on insulator integrated circuits'
[patent_app_type] => new
[patent_app_number] => 09/783869
[patent_app_country] => US
[patent_app_date] => 2001-02-15
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[pdf_file] => publications/A1/0109/20020109189.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/783869 | Method and structure for providing ESD protection for silicon on insulator integrated circuits | Feb 14, 2001 | Abandoned |
Array
(
[id] => 6016385
[patent_doc_number] => 20020102787
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[patent_kind] => A1
[patent_issue_date] => 2002-08-01
[patent_title] => 'Passivation for improved bipolar yield'
[patent_app_type] => new
[patent_app_number] => 09/773798
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/773798 | Passivation for improved bipolar yield | Jan 31, 2001 | Issued |
Array
(
[id] => 1253282
[patent_doc_number] => 06670222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-30
[patent_title] => 'Texturing of a die pad surface for enhancing bonding strength in the surface attachment'
[patent_app_type] => B1
[patent_app_number] => 09/772436
[patent_app_country] => US
[patent_app_date] => 2001-01-29
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/772436 | Texturing of a die pad surface for enhancing bonding strength in the surface attachment | Jan 28, 2001 | Issued |
Array
(
[id] => 1066259
[patent_doc_number] => 06847091
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-25
[patent_title] => 'Vertical semiconductor component having a reduced electrical surface field'
[patent_app_type] => utility
[patent_app_number] => 09/756539
[patent_app_country] => US
[patent_app_date] => 2001-01-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/756539 | Vertical semiconductor component having a reduced electrical surface field | Jan 7, 2001 | Issued |
Array
(
[id] => 6959547
[patent_doc_number] => 20010011739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-09
[patent_title] => 'Ferroelectric random access memory device'
[patent_app_type] => new
[patent_app_number] => 09/746459
[patent_app_country] => US
[patent_app_date] => 2000-12-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/746459 | Ferroelectric random access memory device | Dec 25, 2000 | Abandoned |
Array
(
[id] => 1310388
[patent_doc_number] => 06613611
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'ASIC routing architecture with variable number of custom masks'
[patent_app_type] => B1
[patent_app_number] => 09/747129
[patent_app_country] => US
[patent_app_date] => 2000-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/613/06613611.pdf
[firstpage_image] =>[orig_patent_app_number] => 09747129
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/747129 | ASIC routing architecture with variable number of custom masks | Dec 21, 2000 | Issued |
Array
(
[id] => 1069190
[patent_doc_number] => 06844595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Electrostatic discharge protection circuit with high triggering voltage'
[patent_app_type] => utility
[patent_app_number] => 09/747209
[patent_app_country] => US
[patent_app_date] => 2000-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/844/06844595.pdf
[firstpage_image] =>[orig_patent_app_number] => 09747209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/747209 | Electrostatic discharge protection circuit with high triggering voltage | Dec 21, 2000 | Issued |
Array
(
[id] => 1342585
[patent_doc_number] => 06593838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-15
[patent_title] => 'Planar inductor with segmented conductive plane'
[patent_app_type] => B2
[patent_app_number] => 09/745068
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/745068 | Planar inductor with segmented conductive plane | Dec 18, 2000 | Issued |
Array
(
[id] => 6205400
[patent_doc_number] => 20020070425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'RF power bipolar junction transistor having performance-enhancing emitter structure'
[patent_app_type] => new
[patent_app_number] => 09/736888
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736888 | RF power bipolar junction transistor having performance-enhancing emitter structure | Dec 12, 2000 | Abandoned |
Array
(
[id] => 5981972
[patent_doc_number] => 20020096723
[patent_country] => US
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[patent_issue_date] => 2002-07-25
[patent_title] => 'Transient frequency in dynamic threshold metal-oxide-semiconductor field effect transistors'
[patent_app_type] => new
[patent_app_number] => 09/732249
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/732249 | Transient frequency in dynamic threshold metal-oxide-semiconductor field effect transistors | Dec 6, 2000 | Abandoned |
Array
(
[id] => 1361461
[patent_doc_number] => 06569725
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[patent_title] => 'Thin film transistor array and method for fabricating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/722738 | Thin film transistor array and method for fabricating the same | Nov 27, 2000 | Issued |
Array
(
[id] => 1368735
[patent_doc_number] => 06570234
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[patent_title] => 'Radiation resistant integrated circuit design'
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Array
(
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/675209 | Semiconductor device and method for manufacturing the same | Sep 28, 2000 | Issued |