Search

Christopher D. Birkhimer

Examiner (ID: 14978, Phone: (571)270-1178 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2186, 2136, 2138
Total Applications
636
Issued Applications
458
Pending Applications
64
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8672426 [patent_doc_number] => 20130046964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SYSTEM AND METHOD FOR ZERO PENALTY BRANCH MIS-PREDICTIONS' [patent_app_type] => utility [patent_app_number] => 13/209484 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209484
SYSTEM AND METHOD FOR ZERO PENALTY BRANCH MIS-PREDICTIONS Aug 14, 2011 Abandoned
Array ( [id] => 8661261 [patent_doc_number] => 20130042090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'TEMPORAL SIMT EXECUTION OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/209189 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209189
Temporal SIMT execution optimization through elimination of redundant operations Aug 11, 2011 Issued
Array ( [id] => 8661260 [patent_doc_number] => 20130042089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'WORD LINE LATE KILL IN SCHEDULER' [patent_app_type] => utility [patent_app_number] => 13/207724 [patent_app_country] => US [patent_app_date] => 2011-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13207724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/207724
WORD LINE LATE KILL IN SCHEDULER Aug 10, 2011 Abandoned
Array ( [id] => 8059035 [patent_doc_number] => 20120079254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Debugging of a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 13/137375 [patent_app_country] => US [patent_app_date] => 2011-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10272 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079254.pdf [firstpage_image] =>[orig_patent_app_number] => 13137375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137375
Debug instruction set allocation according to processor operating state Aug 9, 2011 Issued
Array ( [id] => 10143930 [patent_doc_number] => 09176739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions' [patent_app_type] => utility [patent_app_number] => 13/204346 [patent_app_country] => US [patent_app_date] => 2011-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7264 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13204346 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/204346
System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions Aug 4, 2011 Issued
Array ( [id] => 9826020 [patent_doc_number] => 08935516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Enabling portions of programs to be executed on system z integrated information processor (zIIP) without requiring programs to be entirely restructured' [patent_app_type] => utility [patent_app_number] => 13/193761 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4175 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193761 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193761
Enabling portions of programs to be executed on system z integrated information processor (zIIP) without requiring programs to be entirely restructured Jul 28, 2011 Issued
Array ( [id] => 8485082 [patent_doc_number] => 20120284489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Methods and Apparatus for Constant Extension in a Processor' [patent_app_type] => utility [patent_app_number] => 13/155565 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8315 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155565 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155565
Methods and Apparatus for Constant Extension in a Processor Jun 7, 2011 Abandoned
Array ( [id] => 10517724 [patent_doc_number] => 09244772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Computer processor providing error recovery with idempotent regions' [patent_app_type] => utility [patent_app_number] => 13/100517 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5489 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100517
Computer processor providing error recovery with idempotent regions May 3, 2011 Issued
Array ( [id] => 8485081 [patent_doc_number] => 20120284488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Methods and Apparatus for Constant Extension in a Processor' [patent_app_type] => utility [patent_app_number] => 13/099425 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8492 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13099425 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/099425
Methods and Apparatus for Constant Extension in a Processor May 2, 2011 Abandoned
Array ( [id] => 8479187 [patent_doc_number] => 20120278595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'DETERMINING EACH STALL REASON FOR EACH STALLED INSTRUCTION WITHIN A GROUP OF INSTRUCTIONS DURING A PIPELINE STALL' [patent_app_type] => utility [patent_app_number] => 13/097284 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097284 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/097284
Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall Apr 28, 2011 Issued
Array ( [id] => 8479189 [patent_doc_number] => 20120278596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'APPARATUS AND METHOD FOR CHECKPOINT REPAIR IN A PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/094110 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13094110 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/094110
Register renaming scheme with checkpoint repair in a processing device Apr 25, 2011 Issued
Array ( [id] => 8455025 [patent_doc_number] => 20120265971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS' [patent_app_type] => utility [patent_app_number] => 13/088298 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9692 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088298 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088298
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions Apr 14, 2011 Issued
Array ( [id] => 8455020 [patent_doc_number] => 20120265966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'PROCESSOR WITH INCREASED EFFICIENCY VIA EARLY INSTRUCTION COMPLETION' [patent_app_type] => utility [patent_app_number] => 13/088096 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088096
Processor with increased efficiency via early instruction completion Apr 14, 2011 Issued
Array ( [id] => 9392340 [patent_doc_number] => 08688962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Gather cache architecture' [patent_app_type] => utility [patent_app_number] => 13/078380 [patent_app_country] => US [patent_app_date] => 2011-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3818 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13078380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/078380
Gather cache architecture Mar 31, 2011 Issued
Array ( [id] => 7493012 [patent_doc_number] => 20110238965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT PERFORMING THE METHOD' [patent_app_type] => utility [patent_app_number] => 13/052197 [patent_app_country] => US [patent_app_date] => 2011-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7501 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20110238965.pdf [firstpage_image] =>[orig_patent_app_number] => 13052197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/052197
Branch prediction method and branch prediction circuit performing the method Mar 20, 2011 Issued
Array ( [id] => 8337357 [patent_doc_number] => 20120204065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'METHOD FOR GUARANTEEING PROGRAM CORRECTNESS USING FINE-GRAINED HARDWARE SPECULATIVE EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/020228 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5932 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13020228 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020228
Method for guaranteeing program correctness using fine-grained hardware speculative execution Feb 2, 2011 Issued
Array ( [id] => 11465811 [patent_doc_number] => 09582443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-28 [patent_title] => 'Serial control channel processor for executing time-based instructions' [patent_app_type] => utility [patent_app_number] => 13/013274 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4811 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013274 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013274
Serial control channel processor for executing time-based instructions Jan 24, 2011 Issued
Array ( [id] => 8314927 [patent_doc_number] => 20120191952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'PROCESSOR IMPLEMENTING SCALAR CODE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/011637 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13011637 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011637
PROCESSOR IMPLEMENTING SCALAR CODE OPTIMIZATION Jan 20, 2011 Abandoned
Array ( [id] => 8303123 [patent_doc_number] => 20120185679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'Endpoint-Based Parallel Data Processing With Non-Blocking Collective Instructions In A Parallel Active Messaging Interface Of A Parallel Computer' [patent_app_type] => utility [patent_app_number] => 13/007848 [patent_app_country] => US [patent_app_date] => 2011-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007848
Endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface of a parallel computer Jan 16, 2011 Issued
Array ( [id] => 8303107 [patent_doc_number] => 20120185670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SCALAR INTEGER INSTRUCTIONS CAPABLE OF EXECUTION WITH THREE REGISTERS' [patent_app_type] => utility [patent_app_number] => 13/007050 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007050
SCALAR INTEGER INSTRUCTIONS CAPABLE OF EXECUTION WITH THREE REGISTERS Jan 13, 2011 Abandoned
Menu