Search

Christopher D. Birkhimer

Examiner (ID: 14978, Phone: (571)270-1178 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2186, 2136, 2138
Total Applications
636
Issued Applications
458
Pending Applications
64
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14187663 [patent_doc_number] => 20190113536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => Flow Measurement Device for a Structure [patent_app_type] => utility [patent_app_number] => 16/090520 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16090520 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/090520
Flow Measurement Device for a Structure Apr 2, 2017 Abandoned
Array ( [id] => 11731342 [patent_doc_number] => 20170192785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'INSTRUCTION AND LOGIC TO PROVIDE VECTOR COMPRESS AND ROTATE FUNCTIONALITY' [patent_app_type] => utility [patent_app_number] => 15/462392 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 19629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462392
Instruction and logic to provide vector compress and rotate functionality Mar 16, 2017 Issued
Array ( [id] => 15683899 [patent_doc_number] => 20200096613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => LIDAR SYSTEM BASED ON VISIBLE-NEAR INFRARED-SHORTWAVE INFRARED LIGHT BANDS [patent_app_type] => utility [patent_app_number] => 16/305675 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16305675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/305675
LIDAR SYSTEM BASED ON VISIBLE-NEAR INFRARED-SHORTWAVE INFRARED LIGHT BANDS Jan 11, 2017 Abandoned
Array ( [id] => 14825191 [patent_doc_number] => 10409603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory [patent_app_type] => utility [patent_app_number] => 15/396177 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 20444 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396177 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396177
Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory Dec 29, 2016 Issued
Array ( [id] => 11570519 [patent_doc_number] => 20170109163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SIMD VARIABLE SHIFT AND ROTATE USING CONTROL MANIPULATION' [patent_app_type] => utility [patent_app_number] => 15/391695 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18123 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391695 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391695
SIMD variable shift and rotate using control manipulation Dec 26, 2016 Issued
Array ( [id] => 12868666 [patent_doc_number] => 20180181397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD AND APPARATUS TO EFFICIENTLY HANDLE ALLOCATION OF MEMORY ORDERING BUFFERS IN A MULTI-STRAND OUT-OF-ORDER LOOP PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/391791 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391791
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor Dec 26, 2016 Issued
Array ( [id] => 12433497 [patent_doc_number] => 09977680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Clock-gating for multicycle instructions [patent_app_type] => utility [patent_app_number] => 15/282077 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9355 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282077 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282077
Clock-gating for multicycle instructions Sep 29, 2016 Issued
Array ( [id] => 11693110 [patent_doc_number] => 20170168825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'AUXILIARY BRANCH PREDICTION WITH USEFULNESS TRACKING' [patent_app_type] => utility [patent_app_number] => 15/245280 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245280
Auxiliary branch prediction with usefulness tracking Aug 23, 2016 Issued
Array ( [id] => 11530964 [patent_doc_number] => 20170090942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'HETEROGENEOUS CORE MICROARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/242764 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4261 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242764
Heterogeneous core microarchitecture Aug 21, 2016 Issued
Array ( [id] => 14952983 [patent_doc_number] => 10437756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Operation of a multi-slice processor implementing datapath steering [patent_app_type] => utility [patent_app_number] => 15/220780 [patent_app_country] => US [patent_app_date] => 2016-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7154 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220780
Operation of a multi-slice processor implementing datapath steering Jul 26, 2016 Issued
Array ( [id] => 12094430 [patent_doc_number] => 20170351523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING' [patent_app_type] => utility [patent_app_number] => 15/172635 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/172635
Operation of a multi-slice processor implementing datapath steering Jun 2, 2016 Issued
Array ( [id] => 12842971 [patent_doc_number] => 20180172830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => DISTANCE IMAGE PROCESSING DEVICE, DISTANCE IMAGE PROCESSING METHOD, DISTANCE IMAGE PROCESSING PROGRAM, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 15/737032 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15737032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/737032
DISTANCE IMAGE PROCESSING DEVICE, DISTANCE IMAGE PROCESSING METHOD, DISTANCE IMAGE PROCESSING PROGRAM, AND RECORDING MEDIUM May 24, 2016 Abandoned
Array ( [id] => 13817591 [patent_doc_number] => 10185564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Method for managing software threads dependent on condition variables [patent_app_type] => utility [patent_app_number] => 15/141428 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141428
Method for managing software threads dependent on condition variables Apr 27, 2016 Issued
Array ( [id] => 11042449 [patent_doc_number] => 20160239405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'DEBUGGING OF A DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/140514 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10304 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15140514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/140514
Allocating a debug instruction set based on the current operating state in a multi-instruction-set data processing apparatus Apr 27, 2016 Issued
Array ( [id] => 14601035 [patent_doc_number] => 10353710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Techniques for predicting a target address of an indirect branch instruction [patent_app_type] => utility [patent_app_number] => 15/141112 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10667 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141112
Techniques for predicting a target address of an indirect branch instruction Apr 27, 2016 Issued
Array ( [id] => 14735581 [patent_doc_number] => 10387190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => System and method of executing a plurality of threads using thread switching on execution time-out using instruction re-write [patent_app_type] => utility [patent_app_number] => 15/139991 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5528 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139991
System and method of executing a plurality of threads using thread switching on execution time-out using instruction re-write Apr 26, 2016 Issued
Array ( [id] => 11258423 [patent_doc_number] => 09483322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-01 [patent_title] => 'Heterogenous core microarchitecture' [patent_app_type] => utility [patent_app_number] => 15/135779 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4263 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135779
Heterogenous core microarchitecture Apr 21, 2016 Issued
Array ( [id] => 13817599 [patent_doc_number] => 10185568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Annotation logic for dynamic instruction lookahead distance determination [patent_app_type] => utility [patent_app_number] => 15/136123 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15136123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/136123
Annotation logic for dynamic instruction lookahead distance determination Apr 21, 2016 Issued
Array ( [id] => 11745666 [patent_doc_number] => 20170199739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY' [patent_app_type] => utility [patent_app_number] => 15/132230 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132230
Instruction prefetcher dynamically controlled by readily available prefetcher accuracy Apr 17, 2016 Issued
Array ( [id] => 11027384 [patent_doc_number] => 20160224341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'EXTENSIBLE EXECUTION UNIT INTERFACE ARCHITECTURE WITH MULTIPLE DECODE LOGIC AND MULTIPLE EXECUTION UNITS' [patent_app_type] => utility [patent_app_number] => 15/095780 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10703 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095780
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Apr 10, 2016 Issued
Menu