Search

Christopher D. Birkhimer

Examiner (ID: 17609, Phone: (571)270-1178 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2136, 2138, 2186
Total Applications
656
Issued Applications
473
Pending Applications
53
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5684087 [patent_doc_number] => 20060200357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Policy based data shredding for storage controller' [patent_app_type] => utility [patent_app_number] => 11/063809 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2051 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200357.pdf [firstpage_image] =>[orig_patent_app_number] => 11063809 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063809
Policy based data shredding for storage controller Feb 22, 2005 Issued
Array ( [id] => 157624 [patent_doc_number] => 07685354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Multiple-core processor with flexible mapping of processor cores to cache banks' [patent_app_type] => utility [patent_app_number] => 11/063792 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 19046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685354.pdf [firstpage_image] =>[orig_patent_app_number] => 11063792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063792
Multiple-core processor with flexible mapping of processor cores to cache banks Feb 22, 2005 Issued
Array ( [id] => 5896403 [patent_doc_number] => 20060004942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Multiple-core processor with support for multiple virtual processors' [patent_app_type] => utility [patent_app_number] => 11/063793 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19089 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004942.pdf [firstpage_image] =>[orig_patent_app_number] => 11063793 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063793
Multiple-core processor with support for multiple virtual processors Feb 22, 2005 Issued
Array ( [id] => 5621143 [patent_doc_number] => 20060190678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag' [patent_app_type] => utility [patent_app_number] => 11/062974 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8214 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190678.pdf [firstpage_image] =>[orig_patent_app_number] => 11062974 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062974
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag Feb 21, 2005 Abandoned
Array ( [id] => 7052402 [patent_doc_number] => 20050188121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'System and controller with reduced bus utilization time' [patent_app_type] => utility [patent_app_number] => 11/044038 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17316 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188121.pdf [firstpage_image] =>[orig_patent_app_number] => 11044038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044038
System and controller with reduced bus utilization time Jan 27, 2005 Issued
Array ( [id] => 5668878 [patent_doc_number] => 20060174228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Adaptive pre-fetch policy' [patent_app_type] => utility [patent_app_number] => 11/046277 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4332 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174228.pdf [firstpage_image] =>[orig_patent_app_number] => 11046277 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046277
Adaptive pre-fetch policy Jan 27, 2005 Abandoned
Array ( [id] => 5740059 [patent_doc_number] => 20060010450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'System and method for soft partitioning a computer system' [patent_app_type] => utility [patent_app_number] => 11/038379 [patent_app_country] => US [patent_app_date] => 2005-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18087 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010450.pdf [firstpage_image] =>[orig_patent_app_number] => 11038379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038379
System and method for soft partitioning a computer system Jan 19, 2005 Issued
Array ( [id] => 5867039 [patent_doc_number] => 20060101170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Control method for changing input-output object' [patent_app_type] => utility [patent_app_number] => 11/033376 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7490 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101170.pdf [firstpage_image] =>[orig_patent_app_number] => 11033376 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033376
Control method for changing input-output object Jan 11, 2005 Abandoned
Array ( [id] => 5633427 [patent_doc_number] => 20060149898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Apparatus, system, and method for optimizing recall of logical volumes in a virtual tape server' [patent_app_type] => utility [patent_app_number] => 11/029322 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8174 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149898.pdf [firstpage_image] =>[orig_patent_app_number] => 11029322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029322
Apparatus, system, and method for optimizing recall of logical volumes in a virtual tape server Jan 4, 2005 Issued
Array ( [id] => 868793 [patent_doc_number] => 07370174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Method, system, and program for addressing pages of memory by an I/O device' [patent_app_type] => utility [patent_app_number] => 11/029917 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7972 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/370/07370174.pdf [firstpage_image] =>[orig_patent_app_number] => 11029917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029917
Method, system, and program for addressing pages of memory by an I/O device Jan 4, 2005 Issued
Array ( [id] => 5728555 [patent_doc_number] => 20060059316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Method and apparatus for managing write back cache' [patent_app_type] => utility [patent_app_number] => 11/030010 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6675 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20060059316.pdf [firstpage_image] =>[orig_patent_app_number] => 11030010 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030010
Method and apparatus for managing write back cache Jan 4, 2005 Abandoned
Array ( [id] => 5809353 [patent_doc_number] => 20060095709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Storage system management method and device' [patent_app_type] => utility [patent_app_number] => 11/022782 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11802 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095709.pdf [firstpage_image] =>[orig_patent_app_number] => 11022782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022782
Storage system management method and device Dec 27, 2004 Abandoned
Array ( [id] => 5657662 [patent_doc_number] => 20060143398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Method and apparatus for least recently used (LRU) software cache' [patent_app_type] => utility [patent_app_number] => 11/021707 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20060143398.pdf [firstpage_image] =>[orig_patent_app_number] => 11021707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021707
Method and apparatus for least recently used (LRU) software cache Dec 22, 2004 Abandoned
Array ( [id] => 7262013 [patent_doc_number] => 20050144399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Multiprocessor system, and consistency control device and consistency control method in multiprocessor system' [patent_app_type] => utility [patent_app_number] => 11/020008 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8721 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144399.pdf [firstpage_image] =>[orig_patent_app_number] => 11020008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020008
Multiprocessor system, and consistency control device and consistency control method in multiprocessor system Dec 22, 2004 Abandoned
Array ( [id] => 5650928 [patent_doc_number] => 20060136663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Sector-specific access control' [patent_app_type] => utility [patent_app_number] => 11/017705 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3448 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136663.pdf [firstpage_image] =>[orig_patent_app_number] => 11017705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017705
Sector-specific access control Dec 21, 2004 Abandoned
Array ( [id] => 493723 [patent_doc_number] => 07219195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Associative memory with invert result capability' [patent_app_type] => utility [patent_app_number] => 11/018993 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219195.pdf [firstpage_image] =>[orig_patent_app_number] => 11018993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018993
Associative memory with invert result capability Dec 20, 2004 Issued
Array ( [id] => 5650933 [patent_doc_number] => 20060136668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Allocating code objects between faster and slower memories' [patent_app_type] => utility [patent_app_number] => 11/015554 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1609 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136668.pdf [firstpage_image] =>[orig_patent_app_number] => 11015554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015554
Allocating code objects between faster and slower memories Dec 16, 2004 Abandoned
Array ( [id] => 5650923 [patent_doc_number] => 20060136658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'DDR2 SDRAM memory module' [patent_app_type] => utility [patent_app_number] => 11/012197 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136658.pdf [firstpage_image] =>[orig_patent_app_number] => 11012197 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012197
DDR2 SDRAM memory module Dec 15, 2004 Abandoned
Array ( [id] => 362539 [patent_doc_number] => 07487320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Apparatus and system for dynamically allocating main memory among a plurality of applications' [patent_app_type] => utility [patent_app_number] => 11/014529 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5912 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487320.pdf [firstpage_image] =>[orig_patent_app_number] => 11014529 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/014529
Apparatus and system for dynamically allocating main memory among a plurality of applications Dec 14, 2004 Issued
Array ( [id] => 5916470 [patent_doc_number] => 20060129785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Storage of data blocks of logical volumes in a virtual disk storage subsystem' [patent_app_type] => utility [patent_app_number] => 11/013003 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3950 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129785.pdf [firstpage_image] =>[orig_patent_app_number] => 11013003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013003
Storage of data blocks of logical volumes in a virtual disk storage subsystem Dec 14, 2004 Issued
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