Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10438570
[patent_doc_number] => 20150323583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'METHOD FOR DETECTING AN ELECTRICAL DEFECT OF CONTACT/VIA PLUGS'
[patent_app_type] => utility
[patent_app_number] => 14/275437
[patent_app_country] => US
[patent_app_date] => 2014-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2884
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14275437
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/275437 | Method for detecting an electrical defect of contact/via plugs | May 11, 2014 | Issued |
Array
(
[id] => 10343551
[patent_doc_number] => 20150228556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-13
[patent_title] => 'INTEGRATED DEVICE COMPRISING VIA WITH SIDE BARRIER LAYER TRAVERSING ENCAPSULATION LAYER'
[patent_app_type] => utility
[patent_app_number] => 14/274517
[patent_app_country] => US
[patent_app_date] => 2014-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13489
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274517
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/274517 | Integrated device comprising via with side barrier layer traversing encapsulation layer | May 8, 2014 | Issued |
Array
(
[id] => 10440523
[patent_doc_number] => 20150325535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'Method for Processing a Semiconductor Workpiece and Semiconductor Workpiece'
[patent_app_type] => utility
[patent_app_number] => 14/272535
[patent_app_country] => US
[patent_app_date] => 2014-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6760
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272535
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/272535 | Method for processing a semiconductor workpiece and semiconductor workpiece | May 7, 2014 | Issued |
Array
(
[id] => 10440649
[patent_doc_number] => 20150325661
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'SUBSTRATE FOR MOLECULAR BEAM EPITAXY (MBE) HGCDTE GROWTH'
[patent_app_type] => utility
[patent_app_number] => 14/271727
[patent_app_country] => US
[patent_app_date] => 2014-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1820
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271727
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/271727 | Substrate for molecular beam epitaxy (MBE) HgCdTe growth | May 6, 2014 | Issued |
Array
(
[id] => 10440438
[patent_doc_number] => 20150325450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'REWORK AND STRIPPING OF COMPLEX PATTERNING LAYERS USING CHEMICAL MECHANICAL POLISHING'
[patent_app_type] => utility
[patent_app_number] => 14/270565
[patent_app_country] => US
[patent_app_date] => 2014-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3656
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270565
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/270565 | Rework and stripping of complex patterning layers using chemical mechanical polishing | May 5, 2014 | Issued |
Array
(
[id] => 11883629
[patent_doc_number] => 09754810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-05
[patent_title] => 'Method for the production of a wafer with a carrier unit'
[patent_app_type] => utility
[patent_app_number] => 14/888927
[patent_app_country] => US
[patent_app_date] => 2014-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6846
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14888927
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/888927 | Method for the production of a wafer with a carrier unit | May 4, 2014 | Issued |
Array
(
[id] => 10433248
[patent_doc_number] => 20150318260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-05
[patent_title] => 'GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING'
[patent_app_type] => utility
[patent_app_number] => 14/269457
[patent_app_country] => US
[patent_app_date] => 2014-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4393
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269457
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/269457 | Gas-controlled bonding platform for edge defect reduction during wafer bonding | May 4, 2014 | Issued |
Array
(
[id] => 10131951
[patent_doc_number] => 09165793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-20
[patent_title] => 'Making electrical components in handle wafers of integrated circuit packages'
[patent_app_type] => utility
[patent_app_number] => 14/268899
[patent_app_country] => US
[patent_app_date] => 2014-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268899
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/268899 | Making electrical components in handle wafers of integrated circuit packages | May 1, 2014 | Issued |
Array
(
[id] => 10106622
[patent_doc_number] => 09142406
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-09-22
[patent_title] => 'III-N material grown on ErAlN buffer on Si substrate'
[patent_app_type] => utility
[patent_app_number] => 14/269011
[patent_app_country] => US
[patent_app_date] => 2014-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2487
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269011
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/269011 | III-N material grown on ErAlN buffer on Si substrate | May 1, 2014 | Issued |
Array
(
[id] => 10131951
[patent_doc_number] => 09165793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-20
[patent_title] => 'Making electrical components in handle wafers of integrated circuit packages'
[patent_app_type] => utility
[patent_app_number] => 14/268899
[patent_app_country] => US
[patent_app_date] => 2014-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268899
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/268899 | Making electrical components in handle wafers of integrated circuit packages | May 1, 2014 | Issued |
Array
(
[id] => 10131951
[patent_doc_number] => 09165793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-20
[patent_title] => 'Making electrical components in handle wafers of integrated circuit packages'
[patent_app_type] => utility
[patent_app_number] => 14/268899
[patent_app_country] => US
[patent_app_date] => 2014-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268899
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/268899 | Making electrical components in handle wafers of integrated circuit packages | May 1, 2014 | Issued |
Array
(
[id] => 10131951
[patent_doc_number] => 09165793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-20
[patent_title] => 'Making electrical components in handle wafers of integrated circuit packages'
[patent_app_type] => utility
[patent_app_number] => 14/268899
[patent_app_country] => US
[patent_app_date] => 2014-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268899
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/268899 | Making electrical components in handle wafers of integrated circuit packages | May 1, 2014 | Issued |
Array
(
[id] => 10918469
[patent_doc_number] => 20140321488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-30
[patent_title] => 'Tunable Laser With High Thermal Wavelength Tuning Efficiency'
[patent_app_type] => utility
[patent_app_number] => 14/266248
[patent_app_country] => US
[patent_app_date] => 2014-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5486
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266248
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/266248 | Tunable laser with high thermal wavelength tuning efficiency | Apr 29, 2014 | Issued |
Array
(
[id] => 10892872
[patent_doc_number] => 08916484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-23
[patent_title] => 'Remote plasma radical treatment of silicon oxide'
[patent_app_type] => utility
[patent_app_number] => 14/255471
[patent_app_country] => US
[patent_app_date] => 2014-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 8516
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255471
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/255471 | Remote plasma radical treatment of silicon oxide | Apr 16, 2014 | Issued |
Array
(
[id] => 9639435
[patent_doc_number] => 20140217545
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-07
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/251210
[patent_app_country] => US
[patent_app_date] => 2014-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 9595
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251210
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/251210 | Semiconductor device and method for fabricating the same | Apr 10, 2014 | Issued |
Array
(
[id] => 10385229
[patent_doc_number] => 20150270235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-24
[patent_title] => 'DRY-REMOVABLE PROTECTIVE COATINGS'
[patent_app_type] => utility
[patent_app_number] => 14/218767
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7221
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218767
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/218767 | Dry-removable protective coatings | Mar 17, 2014 | Issued |
Array
(
[id] => 10385276
[patent_doc_number] => 20150270284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-24
[patent_title] => 'JUNCTION BUTTING IN SOI TRANSISTOR WITH EMBEDDED SOURCE/DRAIN'
[patent_app_type] => utility
[patent_app_number] => 14/217572
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5462
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217572
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217572 | Junction butting in SOI transistor with embedded source/drain | Mar 17, 2014 | Issued |
Array
(
[id] => 10158510
[patent_doc_number] => 09190293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-17
[patent_title] => 'Even tungsten etch for high aspect ratio trenches'
[patent_app_type] => utility
[patent_app_number] => 14/215417
[patent_app_country] => US
[patent_app_date] => 2014-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 8746
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14215417
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/215417 | Even tungsten etch for high aspect ratio trenches | Mar 16, 2014 | Issued |
Array
(
[id] => 10106671
[patent_doc_number] => 09142454
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-09-22
[patent_title] => 'Semiconductor structure and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 14/215149
[patent_app_country] => US
[patent_app_date] => 2014-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2574
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14215149
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/215149 | Semiconductor structure and method for manufacturing the same | Mar 16, 2014 | Issued |
Array
(
[id] => 10377905
[patent_doc_number] => 20150262912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'Via Corner Engineering in Trench-First Dual Damascene Process'
[patent_app_type] => utility
[patent_app_number] => 14/213329
[patent_app_country] => US
[patent_app_date] => 2014-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4231
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213329
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/213329 | Via corner engineering in trench-first dual damascene process | Mar 13, 2014 | Issued |