Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9844811 [patent_doc_number] => 08946729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Light emitting diode' [patent_app_type] => utility [patent_app_number] => 13/912476 [patent_app_country] => US [patent_app_date] => 2013-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13912476 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/912476
Light emitting diode Jun 6, 2013 Issued
Array ( [id] => 9081538 [patent_doc_number] => 20130267069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/905893 [patent_app_country] => US [patent_app_date] => 2013-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13905893 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/905893
Method of manufacturing a semiconductor device May 29, 2013 Issued
Array ( [id] => 9121533 [patent_doc_number] => 20130288455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'METHOD OF FORMING A FREESTANDING SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 13/853567 [patent_app_country] => US [patent_app_date] => 2013-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7277 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13853567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/853567
Method of forming a freestanding semiconductor wafer Mar 28, 2013 Issued
Array ( [id] => 9081555 [patent_doc_number] => 20130267085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'METHODS FOR FABRICATING A METAL STRUCTURE FOR A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/852346 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2125 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852346 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852346
Methods for fabricating a metal structure for a semiconductor device Mar 27, 2013 Issued
Array ( [id] => 9148457 [patent_doc_number] => 20130302980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'TUNGSTEN FEATURE FILL' [patent_app_type] => utility [patent_app_number] => 13/851885 [patent_app_country] => US [patent_app_date] => 2013-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 26620 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13851885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/851885
Tungsten feature fill Mar 26, 2013 Issued
Array ( [id] => 9081546 [patent_doc_number] => 20130267076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH' [patent_app_type] => utility [patent_app_number] => 13/851442 [patent_app_country] => US [patent_app_date] => 2013-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13851442 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/851442
Wafer dicing used hybrid multi-step laser scribing process with plasma etch Mar 26, 2013 Issued
Array ( [id] => 9054692 [patent_doc_number] => 20130252406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'Techniques for drying and annealing thermoelectric powders' [patent_app_type] => utility [patent_app_number] => 13/849692 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1554 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849692 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/849692
Techniques for drying and annealing thermoelectric powders Mar 24, 2013 Abandoned
Array ( [id] => 9118323 [patent_doc_number] => 20130285245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/849562 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7320 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/849562
MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES Mar 24, 2013 Abandoned
Array ( [id] => 9844142 [patent_doc_number] => 08946057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Laser and plasma etch wafer dicing using UV-curable adhesive film' [patent_app_type] => utility [patent_app_number] => 13/847964 [patent_app_country] => US [patent_app_date] => 2013-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7697 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13847964 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/847964
Laser and plasma etch wafer dicing using UV-curable adhesive film Mar 19, 2013 Issued
Array ( [id] => 9068782 [patent_doc_number] => 20130260538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'METHOD OF MANUFACTURING GALLIUM NITRIDE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/844894 [patent_app_country] => US [patent_app_date] => 2013-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2274 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844894 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844894
METHOD OF MANUFACTURING GALLIUM NITRIDE SUBSTRATE Mar 15, 2013 Abandoned
Array ( [id] => 9662196 [patent_doc_number] => 08809172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Self-aligned patterning for deep implantation in a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 13/839888 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13839888 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/839888
Self-aligned patterning for deep implantation in a semiconductor structure Mar 14, 2013 Issued
Array ( [id] => 9339014 [patent_doc_number] => 20140065796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD' [patent_app_type] => utility [patent_app_number] => 13/835636 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4287 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835636 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835636
Group III nitride wafer and its production method Mar 14, 2013 Issued
Array ( [id] => 9041761 [patent_doc_number] => 20130244399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'METHOD OF FORMING A LAMINATED SEMICONDUCTOR FILM' [patent_app_type] => utility [patent_app_number] => 13/832453 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11119 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832453
Method of forming a laminated semiconductor film Mar 14, 2013 Issued
Array ( [id] => 9068788 [patent_doc_number] => 20130260544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'TECHNIQUE FOR PROCESSING A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/832578 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832578
Technique for processing a substrate Mar 14, 2013 Issued
Array ( [id] => 10844476 [patent_doc_number] => 08871652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Method of manufacturing a semiconductor template' [patent_app_type] => utility [patent_app_number] => 13/834996 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6121 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834996
Method of manufacturing a semiconductor template Mar 14, 2013 Issued
Array ( [id] => 9174535 [patent_doc_number] => 20130316520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS' [patent_app_type] => utility [patent_app_number] => 13/839161 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15539 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13839161 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/839161
Methods of forming contact regions using sacrificial layers Mar 14, 2013 Issued
Array ( [id] => 9503435 [patent_doc_number] => 08741748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-03 [patent_title] => 'Method to grow group III-nitrides on copper using passivation layers' [patent_app_type] => utility [patent_app_number] => 13/836594 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2529 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13836594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/836594
Method to grow group III-nitrides on copper using passivation layers Mar 14, 2013 Issued
Array ( [id] => 9831818 [patent_doc_number] => 08940631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Methods of forming coaxial feedthroughs for 3D integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/843608 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2012 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843608 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/843608
Methods of forming coaxial feedthroughs for 3D integrated circuits Mar 14, 2013 Issued
Array ( [id] => 9094401 [patent_doc_number] => 20130273712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE EMPLOYING TWO RAPID THERMAL ANNEALING PROCESSES, AND RELATED STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/827618 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3713 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13827618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/827618
Process for fabricating a silicon-on-insulator structure employing two rapid thermal annealing processes, and related structures Mar 13, 2013 Issued
Array ( [id] => 9844977 [patent_doc_number] => 08946897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Semiconductor device having metal lines with slits' [patent_app_type] => utility [patent_app_number] => 13/826163 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 10873 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13826163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/826163
Semiconductor device having metal lines with slits Mar 13, 2013 Issued
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