Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10309337 [patent_doc_number] => 20150194338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'Method For Preparing Ultra-thin Material On Insulator Through Adsorption By Doped Ultra-thin Layer' [patent_app_type] => utility [patent_app_number] => 13/825079 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/825079
Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer Sep 24, 2012 Issued
Array ( [id] => 9205507 [patent_doc_number] => 20140004684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'Method for Preparing GOI Chip Structure' [patent_app_type] => utility [patent_app_number] => 13/825010 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4218 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825010 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/825010
Method for preparing GOI chip structure Sep 24, 2012 Issued
Array ( [id] => 8603964 [patent_doc_number] => 20130009276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/616199 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3358 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616199 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/616199
METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES Sep 13, 2012 Abandoned
Array ( [id] => 8519665 [patent_doc_number] => 20120319073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/591891 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3878 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13591891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/591891
Variable resistance memory device having reduced bottom contact area and method of forming the same Aug 21, 2012 Issued
Array ( [id] => 10870203 [patent_doc_number] => 08895399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Integrated circuit and method of forming sealed trench junction termination' [patent_app_type] => utility [patent_app_number] => 13/568410 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 9910 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13568410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/568410
Integrated circuit and method of forming sealed trench junction termination Aug 6, 2012 Issued
Array ( [id] => 8493305 [patent_doc_number] => 20120292714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'STANDARD CELL, SEMICONDUCTOR DEVICE HAVING STANDARD CELLS, AND METHOD FOR LAYING OUT AND WIRING THE STANDARD CELL' [patent_app_type] => utility [patent_app_number] => 13/563205 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12797 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563205 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563205
Standard cell, semiconductor device having standard cells, and method for laying out and wiring the standard cell Jul 30, 2012 Issued
Array ( [id] => 8480842 [patent_doc_number] => 20120280249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS' [patent_app_type] => utility [patent_app_number] => 13/552303 [patent_app_country] => US [patent_app_date] => 2012-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16057 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13552303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/552303
Methods for improving the quality of structures comprising semiconductor materials Jul 17, 2012 Issued
Array ( [id] => 8738811 [patent_doc_number] => 08410582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => '3D polysilicon diode with low contact resistance and method for forming same' [patent_app_type] => utility [patent_app_number] => 13/479093 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9828 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479093
3D polysilicon diode with low contact resistance and method for forming same May 22, 2012 Issued
Array ( [id] => 9435527 [patent_doc_number] => 20140113434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'PROCESS FOR FORMING A CRACK IN A MATERIAL' [patent_app_type] => utility [patent_app_number] => 14/114998 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3616 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14114998 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/114998
Process for forming a crack in a material Apr 26, 2012 Issued
Array ( [id] => 8994911 [patent_doc_number] => 08518795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/455633 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 84 [patent_no_of_words] => 13971 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455633
Method of manufacturing semiconductor device Apr 24, 2012 Issued
13/454985 SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND METHODS TO FORM THE SAME Apr 23, 2012 Abandoned
Array ( [id] => 9269280 [patent_doc_number] => 20140024197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'NONVOLATILE STORAGE ELEMENT AND METHOD OF MANUFACTURING THEREOF' [patent_app_type] => utility [patent_app_number] => 14/110163 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9142 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14110163 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/110163
Nonvolatile storage element and method of manufacturing thereof Apr 10, 2012 Issued
Array ( [id] => 9060473 [patent_doc_number] => 08546912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/440157 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 47 [patent_no_of_words] => 16680 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440157 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440157
Semiconductor device Apr 4, 2012 Issued
Array ( [id] => 9370413 [patent_doc_number] => 20140080286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'METHOD FOR PRODUCING A SEMICONDUCTOR BODY' [patent_app_type] => utility [patent_app_number] => 14/111655 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3044 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14111655 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/111655
Method for producing a semiconductor body Apr 3, 2012 Issued
Array ( [id] => 9227419 [patent_doc_number] => 08633087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Method of manufacturing GaN-based semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/814037 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10288 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13814037 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/814037
Method of manufacturing GaN-based semiconductor device Mar 25, 2012 Issued
Array ( [id] => 8287402 [patent_doc_number] => 20120175729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Discrete Semiconductor Device and Method of Forming Sealed Trench Junction Termination' [patent_app_type] => utility [patent_app_number] => 13/427543 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9795 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427543 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427543
Discrete semiconductor device and method of forming sealed trench junction termination Mar 21, 2012 Issued
Array ( [id] => 8455846 [patent_doc_number] => RE043765 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method for fabricating semiconductor device having trench isolation layer' [patent_app_type] => reissue [patent_app_number] => 13/363073 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1773 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363073 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/363073
Method for fabricating semiconductor device having trench isolation layer Jan 30, 2012 Issued
Array ( [id] => 8192909 [patent_doc_number] => 20120119297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Semiconductor Devices and Methods of Manufacture Thereof' [patent_app_type] => utility [patent_app_number] => 13/355610 [patent_app_country] => US [patent_app_date] => 2012-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119297.pdf [firstpage_image] =>[orig_patent_app_number] => 13355610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/355610
Semiconductor devices and methods of manufacture thereof Jan 22, 2012 Issued
Array ( [id] => 8866144 [patent_doc_number] => 20130149847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'METHOD OF MANUFACTURING GaN-BASED FILM AND COMPOSITE SUBSTRATE USED THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/696873 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 17474 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13696873 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/696873
Method of manufacturing GaN-based film and composite substrate used therefor Dec 20, 2011 Issued
Array ( [id] => 8866148 [patent_doc_number] => 20130149851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'Methods of Protecting Elevated Polysilicon Structures During Etching Processes' [patent_app_type] => utility [patent_app_number] => 13/314270 [patent_app_country] => US [patent_app_date] => 2011-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314270 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/314270
Methods of protecting elevated polysilicon structures during etching processes Dec 7, 2011 Issued
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