Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6600253 [patent_doc_number] => 20100062817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => ' METHOD OF DEFINING A COMMON FRAME OF REFERENCE FOR A VIDEO GAME SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/446614 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20100062817.pdf [firstpage_image] =>[orig_patent_app_number] => 12446614 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/446614
METHOD OF DEFINING A COMMON FRAME OF REFERENCE FOR A VIDEO GAME SYSTEM Oct 23, 2007 Abandoned
Array ( [id] => 6492164 [patent_doc_number] => 20100009735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'METHOD OF DISPLAY ADJUSTMENT FOR A VIDEO GAME SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/446621 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7304 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009735.pdf [firstpage_image] =>[orig_patent_app_number] => 12446621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/446621
METHOD OF DISPLAY ADJUSTMENT FOR A VIDEO GAME SYSTEM Oct 23, 2007 Abandoned
Array ( [id] => 4657708 [patent_doc_number] => 20080026569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Advanced Seed Layers for Interconnects' [patent_app_type] => utility [patent_app_number] => 11/868435 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8231 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026569.pdf [firstpage_image] =>[orig_patent_app_number] => 11868435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868435
Advanced seed layers for interconnects Oct 4, 2007 Issued
Array ( [id] => 5361135 [patent_doc_number] => 20090035929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/905584 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4381 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035929.pdf [firstpage_image] =>[orig_patent_app_number] => 11905584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905584
Method of manufacturing semiconductor device Oct 1, 2007 Abandoned
Array ( [id] => 4803128 [patent_doc_number] => 20080014716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Method for Manufacturing SOI Substrate' [patent_app_type] => utility [patent_app_number] => 11/855736 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014716.pdf [firstpage_image] =>[orig_patent_app_number] => 11855736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855736
Method for manufacturing SOI substrate Sep 13, 2007 Issued
Array ( [id] => 4803129 [patent_doc_number] => 20080014717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Method for Manufacturing SOI Substrate' [patent_app_type] => utility [patent_app_number] => 11/855754 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7249 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014717.pdf [firstpage_image] =>[orig_patent_app_number] => 11855754 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855754
Method for manufacturing SOI substrate Sep 13, 2007 Issued
Array ( [id] => 4446051 [patent_doc_number] => 07863746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Semiconductor device having metal lines with slits' [patent_app_type] => utility [patent_app_number] => 11/882805 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 10827 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863746.pdf [firstpage_image] =>[orig_patent_app_number] => 11882805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/882805
Semiconductor device having metal lines with slits Aug 5, 2007 Issued
Array ( [id] => 8190113 [patent_doc_number] => 08183604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Solid state image pickup device inducing an amplifying MOS transistor having particular conductivity type semiconductor layers, and camera using the same device' [patent_app_type] => utility [patent_app_number] => 11/832329 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4518 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183604.pdf [firstpage_image] =>[orig_patent_app_number] => 11832329 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/832329
Solid state image pickup device inducing an amplifying MOS transistor having particular conductivity type semiconductor layers, and camera using the same device Jul 31, 2007 Issued
Array ( [id] => 4574269 [patent_doc_number] => 07855152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Method of producing active matrix substrate' [patent_app_type] => utility [patent_app_number] => 11/782929 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5679 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855152.pdf [firstpage_image] =>[orig_patent_app_number] => 11782929 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782929
Method of producing active matrix substrate Jul 24, 2007 Issued
Array ( [id] => 4651651 [patent_doc_number] => 20080038907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Method for Fabricating Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 11/782729 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1724 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038907.pdf [firstpage_image] =>[orig_patent_app_number] => 11782729 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782729
Method for Fabricating Non-Volatile Memory Device Jul 24, 2007 Abandoned
Array ( [id] => 4651652 [patent_doc_number] => 20080038908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'METHOD AND SYSTEM FOR CONTINUOUS LARGE-AREA SCANNING IMPLANTATION PROCESS' [patent_app_type] => utility [patent_app_number] => 11/782289 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13355 [patent_no_of_claims] => 119 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038908.pdf [firstpage_image] =>[orig_patent_app_number] => 11782289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782289
Method and system for continuous large-area scanning implantation process Jul 23, 2007 Issued
Array ( [id] => 5521557 [patent_doc_number] => 20090029538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'PROCESS FOR MAKING A SEMICONDUCTOR DEVICE USING PARTIAL ETCHING' [patent_app_type] => utility [patent_app_number] => 11/782319 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029538.pdf [firstpage_image] =>[orig_patent_app_number] => 11782319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782319
Process for making a semiconductor device using partial etching Jul 23, 2007 Issued
Array ( [id] => 5521545 [patent_doc_number] => 20090029526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Method of Exposing Circuit Lateral Interconnect Contacts by Wafer Saw' [patent_app_type] => utility [patent_app_number] => 11/782488 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2108 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029526.pdf [firstpage_image] =>[orig_patent_app_number] => 11782488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782488
Method of exposing circuit lateral interconnect contacts by wafer saw Jul 23, 2007 Issued
Array ( [id] => 4727430 [patent_doc_number] => 20080206974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'FABRICATION OF SEMICONDUCTOR DEVICE HAVING COMPOSITE CONTACT' [patent_app_type] => utility [patent_app_number] => 11/781308 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206974.pdf [firstpage_image] =>[orig_patent_app_number] => 11781308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781308
Fabrication of semiconductor device having composite contact Jul 22, 2007 Issued
Array ( [id] => 5521568 [patent_doc_number] => 20090029549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'METHOD OF SILICIDE FORMATION FOR NANO STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/781599 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1871 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029549.pdf [firstpage_image] =>[orig_patent_app_number] => 11781599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781599
METHOD OF SILICIDE FORMATION FOR NANO STRUCTURES Jul 22, 2007 Abandoned
Array ( [id] => 83528 [patent_doc_number] => 07741200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Formation and treatment of epitaxial layer containing silicon and carbon' [patent_app_type] => utility [patent_app_number] => 11/778212 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8905 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741200.pdf [firstpage_image] =>[orig_patent_app_number] => 11778212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778212
Formation and treatment of epitaxial layer containing silicon and carbon Jul 15, 2007 Issued
Array ( [id] => 5307475 [patent_doc_number] => 20090014756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Method of producing large area SiC substrates' [patent_app_type] => utility [patent_app_number] => 11/826278 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3230 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014756.pdf [firstpage_image] =>[orig_patent_app_number] => 11826278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/826278
Method of producing large area SiC substrates Jul 12, 2007 Issued
Array ( [id] => 4803127 [patent_doc_number] => 20080014715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'DEVICE AND METHOD FOR THE PROCESSING OF WAFERS' [patent_app_type] => utility [patent_app_number] => 11/777699 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5222 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014715.pdf [firstpage_image] =>[orig_patent_app_number] => 11777699 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/777699
DEVICE AND METHOD FOR THE PROCESSING OF WAFERS Jul 12, 2007 Abandoned
Array ( [id] => 7503390 [patent_doc_number] => 08034724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/826228 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 74 [patent_no_of_words] => 26165 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/034/08034724.pdf [firstpage_image] =>[orig_patent_app_number] => 11826228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/826228
Method for manufacturing semiconductor device Jul 12, 2007 Issued
Array ( [id] => 4573871 [patent_doc_number] => 07855104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Structure and method for latchup suppression' [patent_app_type] => utility [patent_app_number] => 11/776738 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4882 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855104.pdf [firstpage_image] =>[orig_patent_app_number] => 11776738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776738
Structure and method for latchup suppression Jul 11, 2007 Issued
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