Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 162265
[patent_doc_number] => 07670886
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method for fabricating polysilicon film'
[patent_app_type] => utility
[patent_app_number] => 11/472858
[patent_app_country] => US
[patent_app_date] => 2006-06-22
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[pdf_file] => patents/07/670/07670886.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/472858 | Method for fabricating polysilicon film | Jun 21, 2006 | Issued |
Array
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[patent_doc_number] => 07482245
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[patent_issue_date] => 2009-01-27
[patent_title] => 'Stress profile modulation in STI gap fill'
[patent_app_type] => utility
[patent_app_number] => 11/471958
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/471958 | Stress profile modulation in STI gap fill | Jun 19, 2006 | Issued |
Array
(
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[patent_issue_date] => 2006-11-16
[patent_title] => 'Semiconductor device and method for manufacturing the same'
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Array
(
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[patent_issue_date] => 2009-02-17
[patent_title] => 'Layer growth using metal film and/or islands'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424999 | Layer growth using metal film and/or islands | Jun 18, 2006 | Issued |
Array
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[patent_title] => 'Method for producing a grid cap with a locally increased dielectric constant'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454468 | Method for producing a grid cap with a locally increased dielectric constant | Jun 15, 2006 | Issued |
Array
(
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[patent_title] => 'Method of manufacturing semiconductor device'
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Array
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[patent_title] => 'Implantation of carbon and/or fluorine in NMOS fabrication'
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[pdf_file] => publications/A1/0287/20070287274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11451919
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451919 | Implantation of carbon and/or fluorine in NMOS fabrication | Jun 12, 2006 | Issued |
Array
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[id] => 585145
[patent_doc_number] => 07442620
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[patent_issue_date] => 2008-10-28
[patent_title] => 'Methods for forming a trench isolation structure with rounded corners in a silicon substrate'
[patent_app_type] => utility
[patent_app_number] => 11/423859
[patent_app_country] => US
[patent_app_date] => 2006-06-13
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[pdf_file] => patents/07/442/07442620.pdf
[firstpage_image] =>[orig_patent_app_number] => 11423859
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/423859 | Methods for forming a trench isolation structure with rounded corners in a silicon substrate | Jun 12, 2006 | Issued |
Array
(
[id] => 4999924
[patent_doc_number] => 20070042558
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[patent_title] => 'Process for manufacturing a high-quality SOI wafer'
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Array
(
[id] => 5697564
[patent_doc_number] => 20060214248
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[patent_issue_date] => 2006-09-28
[patent_title] => 'Single crystal silicon sensor with additional layer and method of producing the same'
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[patent_app_number] => 11/445549
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Array
(
[id] => 5750926
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[patent_title] => 'Methods of fabricating self-aligned source of flash memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/446064 | Methods of fabricating self-aligned source of flash memory device | May 31, 2006 | Abandoned |
Array
(
[id] => 322543
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[patent_title] => 'Methods of selective deposition of heavily doped epitaxial SiGe'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420906 | Methods of selective deposition of heavily doped epitaxial SiGe | May 29, 2006 | Issued |
Array
(
[id] => 5010956
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[patent_title] => 'ENGINEERING STRAIN IN THICK STRAINED-SOI SUBSTRATES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420849 | Engineering strain in thick strained-SOI substrates | May 29, 2006 | Issued |
Array
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Array
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Array
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Array
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Array
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