Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 162265 [patent_doc_number] => 07670886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Method for fabricating polysilicon film' [patent_app_type] => utility [patent_app_number] => 11/472858 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2268 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/670/07670886.pdf [firstpage_image] =>[orig_patent_app_number] => 11472858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/472858
Method for fabricating polysilicon film Jun 21, 2006 Issued
Array ( [id] => 363434 [patent_doc_number] => 07482245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Stress profile modulation in STI gap fill' [patent_app_type] => utility [patent_app_number] => 11/471958 [patent_app_country] => US [patent_app_date] => 2006-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6546 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482245.pdf [firstpage_image] =>[orig_patent_app_number] => 11471958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/471958
Stress profile modulation in STI gap fill Jun 19, 2006 Issued
Array ( [id] => 5730240 [patent_doc_number] => 20060255354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/455950 [patent_app_country] => US [patent_app_date] => 2006-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10841 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255354.pdf [firstpage_image] =>[orig_patent_app_number] => 11455950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/455950
Semiconductor device and method for manufacturing the same Jun 19, 2006 Issued
Array ( [id] => 352605 [patent_doc_number] => 07491626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Layer growth using metal film and/or islands' [patent_app_type] => utility [patent_app_number] => 11/424999 [patent_app_country] => US [patent_app_date] => 2006-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5387 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491626.pdf [firstpage_image] =>[orig_patent_app_number] => 11424999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424999
Layer growth using metal film and/or islands Jun 18, 2006 Issued
Array ( [id] => 5019578 [patent_doc_number] => 20070145544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method for producing a grid cap with a locally increased dielectric constant' [patent_app_type] => utility [patent_app_number] => 11/454468 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4755 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145544.pdf [firstpage_image] =>[orig_patent_app_number] => 11454468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/454468
Method for producing a grid cap with a locally increased dielectric constant Jun 15, 2006 Issued
Array ( [id] => 5141954 [patent_doc_number] => 20070004170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/451519 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004170.pdf [firstpage_image] =>[orig_patent_app_number] => 11451519 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451519
Method of manufacturing semiconductor device Jun 12, 2006 Issued
Array ( [id] => 5165687 [patent_doc_number] => 20070287274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Implantation of carbon and/or fluorine in NMOS fabrication' [patent_app_type] => utility [patent_app_number] => 11/451919 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287274.pdf [firstpage_image] =>[orig_patent_app_number] => 11451919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451919
Implantation of carbon and/or fluorine in NMOS fabrication Jun 12, 2006 Issued
Array ( [id] => 585145 [patent_doc_number] => 07442620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Methods for forming a trench isolation structure with rounded corners in a silicon substrate' [patent_app_type] => utility [patent_app_number] => 11/423859 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3174 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442620.pdf [firstpage_image] =>[orig_patent_app_number] => 11423859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/423859
Methods for forming a trench isolation structure with rounded corners in a silicon substrate Jun 12, 2006 Issued
Array ( [id] => 4999924 [patent_doc_number] => 20070042558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Process for manufacturing a high-quality SOI wafer' [patent_app_type] => utility [patent_app_number] => 11/448589 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3713 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042558.pdf [firstpage_image] =>[orig_patent_app_number] => 11448589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448589
Process for manufacturing a high-quality SOI wafer Jun 5, 2006 Issued
Array ( [id] => 5697564 [patent_doc_number] => 20060214248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Single crystal silicon sensor with additional layer and method of producing the same' [patent_app_type] => utility [patent_app_number] => 11/445549 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214248.pdf [firstpage_image] =>[orig_patent_app_number] => 11445549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/445549
Single crystal silicon sensor with additional layer and method of producing the same Jun 1, 2006 Issued
Array ( [id] => 5750926 [patent_doc_number] => 20060220075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Methods of fabricating self-aligned source of flash memory device' [patent_app_type] => utility [patent_app_number] => 11/446064 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1737 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220075.pdf [firstpage_image] =>[orig_patent_app_number] => 11446064 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/446064
Methods of fabricating self-aligned source of flash memory device May 31, 2006 Abandoned
Array ( [id] => 322543 [patent_doc_number] => 07517775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Methods of selective deposition of heavily doped epitaxial SiGe' [patent_app_type] => utility [patent_app_number] => 11/420906 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 7458 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517775.pdf [firstpage_image] =>[orig_patent_app_number] => 11420906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420906
Methods of selective deposition of heavily doped epitaxial SiGe May 29, 2006 Issued
Array ( [id] => 5010956 [patent_doc_number] => 20070281435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'ENGINEERING STRAIN IN THICK STRAINED-SOI SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/420849 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281435.pdf [firstpage_image] =>[orig_patent_app_number] => 11420849 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420849
Engineering strain in thick strained-SOI substrates May 29, 2006 Issued
Array ( [id] => 579149 [patent_doc_number] => 07452784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Formation of improved SOI substrates using bulk semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/420279 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 42 [patent_no_of_words] => 7575 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 453 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452784.pdf [firstpage_image] =>[orig_patent_app_number] => 11420279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420279
Formation of improved SOI substrates using bulk semiconductor wafers May 24, 2006 Issued
Array ( [id] => 5599589 [patent_doc_number] => 20060289934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/438846 [patent_app_country] => US [patent_app_date] => 2006-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9827 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20060289934.pdf [firstpage_image] =>[orig_patent_app_number] => 11438846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438846
Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device May 22, 2006 Abandoned
Array ( [id] => 4476857 [patent_doc_number] => 07868320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/438066 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 51 [patent_no_of_words] => 20224 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/868/07868320.pdf [firstpage_image] =>[orig_patent_app_number] => 11438066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438066
Semiconductor device and manufacturing method thereof May 21, 2006 Issued
Array ( [id] => 224890 [patent_doc_number] => 07605073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures' [patent_app_type] => utility [patent_app_number] => 11/437319 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3134 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605073.pdf [firstpage_image] =>[orig_patent_app_number] => 11437319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437319
Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures May 18, 2006 Issued
Array ( [id] => 170561 [patent_doc_number] => 07662697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method of forming isolation structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/416738 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 3703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/662/07662697.pdf [firstpage_image] =>[orig_patent_app_number] => 11416738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416738
Method of forming isolation structure of semiconductor device May 1, 2006 Issued
Array ( [id] => 612713 [patent_doc_number] => 07148110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Local-length nitride SONOS device having self-aligned ONO structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/415466 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5370 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148110.pdf [firstpage_image] =>[orig_patent_app_number] => 11415466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/415466
Local-length nitride SONOS device having self-aligned ONO structure and method of manufacturing the same Apr 30, 2006 Issued
Array ( [id] => 4982956 [patent_doc_number] => 20070087514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'SOI substrate with selective oxide layer thickness control' [patent_app_type] => utility [patent_app_number] => 11/411828 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3196 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087514.pdf [firstpage_image] =>[orig_patent_app_number] => 11411828 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/411828
SOI substrate with selective oxide layer thickness control Apr 26, 2006 Abandoned
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