Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 459704
[patent_doc_number] => 07241634
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-10
[patent_title] => 'Semiconductor device and method for producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/412165
[patent_app_country] => US
[patent_app_date] => 2006-04-26
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/241/07241634.pdf
[firstpage_image] =>[orig_patent_app_number] => 11412165
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/412165 | Semiconductor device and method for producing the same | Apr 25, 2006 | Issued |
Array
(
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[patent_doc_number] => 08304322
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-06
[patent_title] => 'Methods of filling isolation trenches for semiconductor devices and resulting structures'
[patent_app_type] => utility
[patent_app_number] => 11/405629
[patent_app_country] => US
[patent_app_date] => 2006-04-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/405629 | Methods of filling isolation trenches for semiconductor devices and resulting structures | Apr 17, 2006 | Issued |
Array
(
[id] => 5608686
[patent_doc_number] => 20060270202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING A VERTICAL DOPANT PROFILE'
[patent_app_type] => utility
[patent_app_number] => 11/379079
[patent_app_country] => US
[patent_app_date] => 2006-04-18
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[pdf_file] => publications/A1/0270/20060270202.pdf
[firstpage_image] =>[orig_patent_app_number] => 11379079
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/379079 | TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING A VERTICAL DOPANT PROFILE | Apr 17, 2006 | Abandoned |
Array
(
[id] => 5675523
[patent_doc_number] => 20060180878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-17
[patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode'
[patent_app_type] => utility
[patent_app_number] => 11/393151
[patent_app_country] => US
[patent_app_date] => 2006-03-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/393151 | Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode | Mar 28, 2006 | Issued |
Array
(
[id] => 5125989
[patent_doc_number] => 20070238260
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[patent_issue_date] => 2007-10-11
[patent_title] => 'Method for Forming Shallow Trench Isolation Region'
[patent_app_type] => utility
[patent_app_number] => 11/277678
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[patent_app_date] => 2006-03-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/277678 | Method for forming shallow trench isolation region | Mar 27, 2006 | Issued |
Array
(
[id] => 5700198
[patent_doc_number] => 20060216883
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[patent_issue_date] => 2006-09-28
[patent_title] => 'Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated'
[patent_app_type] => utility
[patent_app_number] => 11/386299
[patent_app_country] => US
[patent_app_date] => 2006-03-21
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[firstpage_image] =>[orig_patent_app_number] => 11386299
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/386299 | Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated | Mar 20, 2006 | Issued |
Array
(
[id] => 5063132
[patent_doc_number] => 20070224772
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[patent_issue_date] => 2007-09-27
[patent_title] => 'Method for forming a stressor structure'
[patent_app_type] => utility
[patent_app_number] => 11/386539
[patent_app_country] => US
[patent_app_date] => 2006-03-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0224/20070224772.pdf
[firstpage_image] =>[orig_patent_app_number] => 11386539
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/386539 | Method for forming a stressor structure | Mar 20, 2006 | Abandoned |
Array
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[patent_doc_number] => 20060223280
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[patent_issue_date] => 2006-10-05
[patent_title] => 'Method for manufacturing semiconductor device and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/376189
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[patent_app_date] => 2006-03-16
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[firstpage_image] =>[orig_patent_app_number] => 11376189
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/376189 | Method for manufacturing semiconductor device and semiconductor device | Mar 15, 2006 | Abandoned |
Array
(
[id] => 5760324
[patent_doc_number] => 20060211269
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[patent_title] => 'Semiconductor device and its fabrication method'
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[patent_app_number] => 11/376089
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/376089 | Semiconductor device and its fabrication method | Mar 15, 2006 | Abandoned |
Array
(
[id] => 4977428
[patent_doc_number] => 20070218661
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[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility'
[patent_app_type] => utility
[patent_app_number] => 11/375768
[patent_app_country] => US
[patent_app_date] => 2006-03-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/375768 | Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility | Mar 14, 2006 | Issued |
Array
(
[id] => 373317
[patent_doc_number] => 07473620
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[patent_issue_date] => 2009-01-06
[patent_title] => 'Process for adjusting the strain on the surface or inside a substrate made of a semiconductor material'
[patent_app_type] => utility
[patent_app_number] => 11/372868
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/372868 | Process for adjusting the strain on the surface or inside a substrate made of a semiconductor material | Mar 9, 2006 | Issued |
Array
(
[id] => 369848
[patent_doc_number] => 07476621
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[patent_issue_date] => 2009-01-13
[patent_title] => 'Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill'
[patent_app_type] => utility
[patent_app_number] => 11/366220
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/366220 | Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill | Feb 28, 2006 | Issued |
Array
(
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[patent_title] => 'Method of manufacturing semiconductor device and semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/363999 | Method of manufacturing semiconductor device and semiconductor device | Feb 28, 2006 | Issued |
Array
(
[id] => 369844
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[patent_title] => 'Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same'
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[patent_app_number] => 11/361526
[patent_app_country] => US
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Array
(
[id] => 5675486
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[patent_title] => 'eDRAM-type semiconductor device including logic circuit section featuring large capacitance capacitor, and capacitor DRAM section featuring small capacitance capacitor'
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Array
(
[id] => 5652795
[patent_doc_number] => 20060138530
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[patent_title] => 'Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell'
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[patent_app_number] => 11/357287
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Array
(
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[patent_title] => 'Semiconductor devices having regions of induced high and low conductivity, and methods of making the same'
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Array
(
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Array
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Array
(
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[patent_title] => 'LOCOS self-aligned twin well with a co-planar silicon surface'
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