Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 459704 [patent_doc_number] => 07241634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Semiconductor device and method for producing the same' [patent_app_type] => utility [patent_app_number] => 11/412165 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5454 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/241/07241634.pdf [firstpage_image] =>[orig_patent_app_number] => 11412165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412165
Semiconductor device and method for producing the same Apr 25, 2006 Issued
Array ( [id] => 8527752 [patent_doc_number] => 08304322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Methods of filling isolation trenches for semiconductor devices and resulting structures' [patent_app_type] => utility [patent_app_number] => 11/405629 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 3358 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11405629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/405629
Methods of filling isolation trenches for semiconductor devices and resulting structures Apr 17, 2006 Issued
Array ( [id] => 5608686 [patent_doc_number] => 20060270202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING A VERTICAL DOPANT PROFILE' [patent_app_type] => utility [patent_app_number] => 11/379079 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8350 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20060270202.pdf [firstpage_image] =>[orig_patent_app_number] => 11379079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379079
TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING A VERTICAL DOPANT PROFILE Apr 17, 2006 Abandoned
Array ( [id] => 5675523 [patent_doc_number] => 20060180878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode' [patent_app_type] => utility [patent_app_number] => 11/393151 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5143 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20060180878.pdf [firstpage_image] =>[orig_patent_app_number] => 11393151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/393151
Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode Mar 28, 2006 Issued
Array ( [id] => 5125989 [patent_doc_number] => 20070238260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Method for Forming Shallow Trench Isolation Region' [patent_app_type] => utility [patent_app_number] => 11/277678 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20070238260.pdf [firstpage_image] =>[orig_patent_app_number] => 11277678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277678
Method for forming shallow trench isolation region Mar 27, 2006 Issued
Array ( [id] => 5700198 [patent_doc_number] => 20060216883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated' [patent_app_type] => utility [patent_app_number] => 11/386299 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9321 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20060216883.pdf [firstpage_image] =>[orig_patent_app_number] => 11386299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386299
Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated Mar 20, 2006 Issued
Array ( [id] => 5063132 [patent_doc_number] => 20070224772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Method for forming a stressor structure' [patent_app_type] => utility [patent_app_number] => 11/386539 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20070224772.pdf [firstpage_image] =>[orig_patent_app_number] => 11386539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386539
Method for forming a stressor structure Mar 20, 2006 Abandoned
Array ( [id] => 5754131 [patent_doc_number] => 20060223280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Method for manufacturing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/376189 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5468 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20060223280.pdf [firstpage_image] =>[orig_patent_app_number] => 11376189 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376189
Method for manufacturing semiconductor device and semiconductor device Mar 15, 2006 Abandoned
Array ( [id] => 5760324 [patent_doc_number] => 20060211269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Semiconductor device and its fabrication method' [patent_app_type] => utility [patent_app_number] => 11/376089 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4390 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211269.pdf [firstpage_image] =>[orig_patent_app_number] => 11376089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376089
Semiconductor device and its fabrication method Mar 15, 2006 Abandoned
Array ( [id] => 4977428 [patent_doc_number] => 20070218661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility' [patent_app_type] => utility [patent_app_number] => 11/375768 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218661.pdf [firstpage_image] =>[orig_patent_app_number] => 11375768 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/375768
Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility Mar 14, 2006 Issued
Array ( [id] => 373317 [patent_doc_number] => 07473620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Process for adjusting the strain on the surface or inside a substrate made of a semiconductor material' [patent_app_type] => utility [patent_app_number] => 11/372868 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 3280 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473620.pdf [firstpage_image] =>[orig_patent_app_number] => 11372868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/372868
Process for adjusting the strain on the surface or inside a substrate made of a semiconductor material Mar 9, 2006 Issued
Array ( [id] => 369848 [patent_doc_number] => 07476621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-13 [patent_title] => 'Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill' [patent_app_type] => utility [patent_app_number] => 11/366220 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6038 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476621.pdf [firstpage_image] =>[orig_patent_app_number] => 11366220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/366220
Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill Feb 28, 2006 Issued
Array ( [id] => 5754140 [patent_doc_number] => 20060223289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Method of manufacturing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/363999 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3752 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20060223289.pdf [firstpage_image] =>[orig_patent_app_number] => 11363999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363999
Method of manufacturing semiconductor device and semiconductor device Feb 28, 2006 Issued
Array ( [id] => 369844 [patent_doc_number] => 07476617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/361526 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 6175 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476617.pdf [firstpage_image] =>[orig_patent_app_number] => 11361526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/361526
Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same Feb 23, 2006 Issued
Array ( [id] => 5675486 [patent_doc_number] => 20060180841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'eDRAM-type semiconductor device including logic circuit section featuring large capacitance capacitor, and capacitor DRAM section featuring small capacitance capacitor' [patent_app_type] => utility [patent_app_number] => 11/356006 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20060180841.pdf [firstpage_image] =>[orig_patent_app_number] => 11356006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356006
eDRAM-type semiconductor device including logic circuit section featuring large capacitance capacitor, and capacitor DRAM section featuring small capacitance capacitor Feb 16, 2006 Issued
Array ( [id] => 5652795 [patent_doc_number] => 20060138530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell' [patent_app_type] => utility [patent_app_number] => 11/357287 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5504 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138530.pdf [firstpage_image] =>[orig_patent_app_number] => 11357287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357287
Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell Feb 15, 2006 Issued
Array ( [id] => 122612 [patent_doc_number] => 07704784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Semiconductor devices having regions of induced high and low conductivity, and methods of making the same' [patent_app_type] => utility [patent_app_number] => 11/354365 [patent_app_country] => US [patent_app_date] => 2006-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15783 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704784.pdf [firstpage_image] =>[orig_patent_app_number] => 11354365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354365
Semiconductor devices having regions of induced high and low conductivity, and methods of making the same Feb 14, 2006 Issued
Array ( [id] => 879837 [patent_doc_number] => 07354844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Method for manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 11/346639 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 7233 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/354/07354844.pdf [firstpage_image] =>[orig_patent_app_number] => 11346639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346639
Method for manufacturing SOI substrate Feb 2, 2006 Issued
Array ( [id] => 5649086 [patent_doc_number] => 20060134821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Manufacturing method of a microelectromechanical switch' [patent_app_type] => utility [patent_app_number] => 11/343400 [patent_app_country] => US [patent_app_date] => 2006-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5145 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134821.pdf [firstpage_image] =>[orig_patent_app_number] => 11343400 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/343400
Manufacturing method of a microelectromechanical switch Jan 30, 2006 Issued
Array ( [id] => 190870 [patent_doc_number] => 07642181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'LOCOS self-aligned twin well with a co-planar silicon surface' [patent_app_type] => utility [patent_app_number] => 11/343179 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 6091 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642181.pdf [firstpage_image] =>[orig_patent_app_number] => 11343179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/343179
LOCOS self-aligned twin well with a co-planar silicon surface Jan 29, 2006 Issued
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