Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5034894
[patent_doc_number] => 20070099433
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'GAS DIELECTRIC STRUCTURE FORMATION USING RADIATION'
[patent_app_type] => utility
[patent_app_number] => 11/163909
[patent_app_country] => US
[patent_app_date] => 2005-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0099/20070099433.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163909
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163909 | GAS DIELECTRIC STRUCTURE FORMATION USING RADIATION | Nov 2, 2005 | Abandoned |
Array
(
[id] => 587244
[patent_doc_number] => 07439159
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-21
[patent_title] => 'Fusion bonding process and structure for fabricating silicon-on-insulator (SOI) semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/262179
[patent_app_country] => US
[patent_app_date] => 2005-10-28
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[pdf_file] => patents/07/439/07439159.pdf
[firstpage_image] =>[orig_patent_app_number] => 11262179
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/262179 | Fusion bonding process and structure for fabricating silicon-on-insulator (SOI) semiconductor devices | Oct 27, 2005 | Issued |
Array
(
[id] => 5034852
[patent_doc_number] => 20070099391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods'
[patent_app_type] => utility
[patent_app_number] => 11/262128
[patent_app_country] => US
[patent_app_date] => 2005-10-28
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[firstpage_image] =>[orig_patent_app_number] => 11262128
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/262128 | Methods for forming semiconductor structures with buried isolation collars | Oct 27, 2005 | Issued |
Array
(
[id] => 5724184
[patent_doc_number] => 20060054944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Semiconductor device and process for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/260197
[patent_app_country] => US
[patent_app_date] => 2005-10-28
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[firstpage_image] =>[orig_patent_app_number] => 11260197
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Array
(
[id] => 369855
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[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Metal oxide layer formed on substrates and its fabrication methods'
[patent_app_type] => utility
[patent_app_number] => 11/258008
[patent_app_country] => US
[patent_app_date] => 2005-10-26
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[pdf_file] => patents/07/476/07476628.pdf
[firstpage_image] =>[orig_patent_app_number] => 11258008
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258008 | Metal oxide layer formed on substrates and its fabrication methods | Oct 25, 2005 | Issued |
Array
(
[id] => 565332
[patent_doc_number] => 07465644
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[patent_kind] => B1
[patent_issue_date] => 2008-12-16
[patent_title] => 'Isolation region bird\'s beak suppression'
[patent_app_type] => utility
[patent_app_number] => 11/258209
[patent_app_country] => US
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[pdf_file] => patents/07/465/07465644.pdf
[firstpage_image] =>[orig_patent_app_number] => 11258209
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258209 | Isolation region bird's beak suppression | Oct 25, 2005 | Issued |
Array
(
[id] => 373329
[patent_doc_number] => 07473632
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[patent_issue_date] => 2009-01-06
[patent_title] => 'Semiconductor device with an air gap between lower interconnections and a connection portion to the lower interconnections not formed adjacent to the air gap'
[patent_app_type] => utility
[patent_app_number] => 11/253568
[patent_app_country] => US
[patent_app_date] => 2005-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/07/473/07473632.pdf
[firstpage_image] =>[orig_patent_app_number] => 11253568
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/253568 | Semiconductor device with an air gap between lower interconnections and a connection portion to the lower interconnections not formed adjacent to the air gap | Oct 19, 2005 | Issued |
Array
(
[id] => 860307
[patent_doc_number] => 07371657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-13
[patent_title] => 'Method for forming an isolating trench with a dielectric material'
[patent_app_type] => utility
[patent_app_number] => 11/252878
[patent_app_country] => US
[patent_app_date] => 2005-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3734
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[pdf_file] => patents/07/371/07371657.pdf
[firstpage_image] =>[orig_patent_app_number] => 11252878
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/252878 | Method for forming an isolating trench with a dielectric material | Oct 18, 2005 | Issued |
Array
(
[id] => 5880985
[patent_doc_number] => 20060030068
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[patent_issue_date] => 2006-02-09
[patent_title] => 'Fabrication method for phase change diode memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/253233
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[patent_app_date] => 2005-10-17
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[pdf_file] => publications/A1/0030/20060030068.pdf
[firstpage_image] =>[orig_patent_app_number] => 11253233
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/253233 | Fabrication method for phase change diode memory cells | Oct 16, 2005 | Issued |
Array
(
[id] => 876282
[patent_doc_number] => 07358198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-15
[patent_title] => 'Semiconductor device and method for fabricating same'
[patent_app_type] => utility
[patent_app_number] => 11/250439
[patent_app_country] => US
[patent_app_date] => 2005-10-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/250439 | Semiconductor device and method for fabricating same | Oct 16, 2005 | Issued |
Array
(
[id] => 4982965
[patent_doc_number] => 20070087523
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[patent_title] => 'Recessed shallow trench isolation'
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[patent_app_number] => 11/249228
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[firstpage_image] =>[orig_patent_app_number] => 11249228
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/249228 | Recessed shallow trench isolation | Oct 12, 2005 | Issued |
Array
(
[id] => 5591009
[patent_doc_number] => 20060040461
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[patent_title] => 'Method of forming a capacitor'
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[firstpage_image] =>[orig_patent_app_number] => 11248311
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/248311 | Method of forming a capacitor | Oct 11, 2005 | Abandoned |
Array
(
[id] => 5800657
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Array
(
[id] => 5878132
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[patent_title] => 'Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/247495 | Semiconductor assemblies having electrophoretically insulated vias | Oct 9, 2005 | Issued |
Array
(
[id] => 5727060
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[patent_title] => 'Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/245251 | Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device | Oct 5, 2005 | Issued |
Array
(
[id] => 5820660
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[patent_title] => 'Methods of etching a contact opening over a node location on a semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 11/237433
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/237433 | Methods of etching a contact opening over a node location on a semiconductor substrate | Sep 27, 2005 | Abandoned |
Array
(
[id] => 352594
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[patent_issue_date] => 2009-02-17
[patent_title] => 'Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162798 | Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors | Sep 22, 2005 | Issued |
Array
(
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[patent_title] => 'Method for forming spacers between bitlines in virtual ground memory array and related structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/227749 | Method for forming spacers between bitlines in virtual ground memory array and related structure | Sep 14, 2005 | Abandoned |
Array
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[patent_title] => 'Memory resistance film with controlled oxygen content'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226998 | Memory resistance film with controlled oxygen content | Sep 13, 2005 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/222613 | Method of manufacturing a transistor and a method of forming a memory device with isolation trenches | Sep 8, 2005 | Issued |