Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5738624 [patent_doc_number] => 20060009015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus' [patent_app_type] => utility [patent_app_number] => 11/221773 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18761 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20060009015.pdf [firstpage_image] =>[orig_patent_app_number] => 11221773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221773
Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus Sep 8, 2005 Issued
Array ( [id] => 5148924 [patent_doc_number] => 20070048984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Metal work function adjustment by ion implantation' [patent_app_type] => utility [patent_app_number] => 11/217699 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4455 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20070048984.pdf [firstpage_image] =>[orig_patent_app_number] => 11217699 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217699
Metal work function adjustment by ion implantation Aug 30, 2005 Abandoned
Array ( [id] => 5892623 [patent_doc_number] => 20060001160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Surface treatment of metal interconnect lines' [patent_app_type] => utility [patent_app_number] => 11/213238 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2473 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001160.pdf [firstpage_image] =>[orig_patent_app_number] => 11213238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213238
Surface treatment of metal interconnect lines Aug 25, 2005 Issued
Array ( [id] => 5222869 [patent_doc_number] => 20070252135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Nitride Semiconductor Light Emitting Device and Fabrication Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/661186 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5972 [patent_no_of_claims] => 94 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20070252135.pdf [firstpage_image] =>[orig_patent_app_number] => 11661186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/661186
Nitride semiconductor light emitting device and fabrication method thereof Aug 18, 2005 Issued
Array ( [id] => 5800624 [patent_doc_number] => 20060035436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Method for producing an n-doped field stop zone in a semiconductor body and semiconductor component having a field stop zone' [patent_app_type] => utility [patent_app_number] => 11/201879 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20060035436.pdf [firstpage_image] =>[orig_patent_app_number] => 11201879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201879
Method for producing an n-doped field stop zone in a semiconductor body and semiconductor component having a field stop zone Aug 10, 2005 Issued
Array ( [id] => 5807859 [patent_doc_number] => 20060094214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Semiconductor doping process' [patent_app_type] => utility [patent_app_number] => 11/199159 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1083 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20060094214.pdf [firstpage_image] =>[orig_patent_app_number] => 11199159 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199159
Semiconductor doping process Aug 8, 2005 Abandoned
Array ( [id] => 5154520 [patent_doc_number] => 20070037403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/161599 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037403.pdf [firstpage_image] =>[orig_patent_app_number] => 11161599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161599
VIA bottom contact and method of manufacturing same Aug 8, 2005 Issued
Array ( [id] => 6931271 [patent_doc_number] => 20050282306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device' [patent_app_type] => utility [patent_app_number] => 11/196967 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 23550 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282306.pdf [firstpage_image] =>[orig_patent_app_number] => 11196967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196967
Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device Aug 3, 2005 Issued
Array ( [id] => 847161 [patent_doc_number] => 07384861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Strain modulation employing process techniques for CMOS technologies' [patent_app_type] => utility [patent_app_number] => 11/183348 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 9022 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/384/07384861.pdf [firstpage_image] =>[orig_patent_app_number] => 11183348 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183348
Strain modulation employing process techniques for CMOS technologies Jul 17, 2005 Issued
Array ( [id] => 928517 [patent_doc_number] => 07314827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/181908 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3365 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/314/07314827.pdf [firstpage_image] =>[orig_patent_app_number] => 11181908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181908
Method of manufacturing semiconductor device Jul 14, 2005 Issued
Array ( [id] => 7043330 [patent_doc_number] => 20050247925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Methods of forming assemblies displaying differential negative resistance' [patent_app_type] => utility [patent_app_number] => 11/181879 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3935 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20050247925.pdf [firstpage_image] =>[orig_patent_app_number] => 11181879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181879
Methods of forming assemblies displaying differential negative resistance Jul 14, 2005 Issued
Array ( [id] => 4568357 [patent_doc_number] => 07858428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-28 [patent_title] => 'Method for forming a lens using sub-micron horizontal tip feature' [patent_app_type] => utility [patent_app_number] => 11/179059 [patent_app_country] => US [patent_app_date] => 2005-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3444 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/858/07858428.pdf [firstpage_image] =>[orig_patent_app_number] => 11179059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179059
Method for forming a lens using sub-micron horizontal tip feature Jul 10, 2005 Issued
Array ( [id] => 861398 [patent_doc_number] => 07372156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Method to fabricate aligned dual damascene openings' [patent_app_type] => utility [patent_app_number] => 11/174805 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2093 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372156.pdf [firstpage_image] =>[orig_patent_app_number] => 11174805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174805
Method to fabricate aligned dual damascene openings Jul 4, 2005 Issued
Array ( [id] => 856743 [patent_doc_number] => 07375002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'MIM capacitor in a semiconductor device and method therefor' [patent_app_type] => utility [patent_app_number] => 11/168579 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2575 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375002.pdf [firstpage_image] =>[orig_patent_app_number] => 11168579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/168579
MIM capacitor in a semiconductor device and method therefor Jun 27, 2005 Issued
Array ( [id] => 817075 [patent_doc_number] => 07410883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Glass-based semiconductor on insulator structures and methods of making same' [patent_app_type] => utility [patent_app_number] => 11/159889 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6588 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410883.pdf [firstpage_image] =>[orig_patent_app_number] => 11159889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159889
Glass-based semiconductor on insulator structures and methods of making same Jun 22, 2005 Issued
Array ( [id] => 5602508 [patent_doc_number] => 20060292853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Method for fabricating an integrated semiconductor circuit and semiconductor circuit' [patent_app_type] => utility [patent_app_number] => 11/158318 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5979 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292853.pdf [firstpage_image] =>[orig_patent_app_number] => 11158318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158318
Method for fabricating an integrated semiconductor circuit and semiconductor circuit Jun 21, 2005 Abandoned
Array ( [id] => 868234 [patent_doc_number] => 07365005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-29 [patent_title] => 'Method for filling of a recessed structure of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/159999 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 14096 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/365/07365005.pdf [firstpage_image] =>[orig_patent_app_number] => 11159999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159999
Method for filling of a recessed structure of a semiconductor device Jun 21, 2005 Issued
Array ( [id] => 8005875 [patent_doc_number] => 08084338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/155668 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 8225 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/084/08084338.pdf [firstpage_image] =>[orig_patent_app_number] => 11155668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/155668
Semiconductor device and manufacturing method thereof Jun 19, 2005 Issued
Array ( [id] => 5785644 [patent_doc_number] => 20060205173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Methods for forming isolation films' [patent_app_type] => utility [patent_app_number] => 11/156998 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2459 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205173.pdf [firstpage_image] =>[orig_patent_app_number] => 11156998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156998
Methods for forming trench isolation Jun 19, 2005 Issued
Array ( [id] => 267104 [patent_doc_number] => 07566629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Patterned silicon-on-insulator layers and methods for forming the same' [patent_app_type] => utility [patent_app_number] => 11/155029 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 9795 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566629.pdf [firstpage_image] =>[orig_patent_app_number] => 11155029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/155029
Patterned silicon-on-insulator layers and methods for forming the same Jun 15, 2005 Issued
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