Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5738624
[patent_doc_number] => 20060009015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/221773
[patent_app_country] => US
[patent_app_date] => 2005-09-09
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[pdf_file] => publications/A1/0009/20060009015.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/221773 | Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus | Sep 8, 2005 | Issued |
Array
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[patent_doc_number] => 20070048984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Metal work function adjustment by ion implantation'
[patent_app_type] => utility
[patent_app_number] => 11/217699
[patent_app_country] => US
[patent_app_date] => 2005-08-31
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[firstpage_image] =>[orig_patent_app_number] => 11217699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/217699 | Metal work function adjustment by ion implantation | Aug 30, 2005 | Abandoned |
Array
(
[id] => 5892623
[patent_doc_number] => 20060001160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'Surface treatment of metal interconnect lines'
[patent_app_type] => utility
[patent_app_number] => 11/213238
[patent_app_country] => US
[patent_app_date] => 2005-08-26
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[firstpage_image] =>[orig_patent_app_number] => 11213238
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/213238 | Surface treatment of metal interconnect lines | Aug 25, 2005 | Issued |
Array
(
[id] => 5222869
[patent_doc_number] => 20070252135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'Nitride Semiconductor Light Emitting Device and Fabrication Method Thereof'
[patent_app_type] => utility
[patent_app_number] => 11/661186
[patent_app_country] => US
[patent_app_date] => 2005-08-19
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[patent_drawing_sheets_cnt] => 8
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[firstpage_image] =>[orig_patent_app_number] => 11661186
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/661186 | Nitride semiconductor light emitting device and fabrication method thereof | Aug 18, 2005 | Issued |
Array
(
[id] => 5800624
[patent_doc_number] => 20060035436
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[patent_issue_date] => 2006-02-16
[patent_title] => 'Method for producing an n-doped field stop zone in a semiconductor body and semiconductor component having a field stop zone'
[patent_app_type] => utility
[patent_app_number] => 11/201879
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/201879 | Method for producing an n-doped field stop zone in a semiconductor body and semiconductor component having a field stop zone | Aug 10, 2005 | Issued |
Array
(
[id] => 5807859
[patent_doc_number] => 20060094214
[patent_country] => US
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[patent_issue_date] => 2006-05-04
[patent_title] => 'Semiconductor doping process'
[patent_app_type] => utility
[patent_app_number] => 11/199159
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/199159 | Semiconductor doping process | Aug 8, 2005 | Abandoned |
Array
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[id] => 5154520
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[patent_title] => 'VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/161599
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[firstpage_image] =>[orig_patent_app_number] => 11161599
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161599 | VIA bottom contact and method of manufacturing same | Aug 8, 2005 | Issued |
Array
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[id] => 6931271
[patent_doc_number] => 20050282306
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[patent_issue_date] => 2005-12-22
[patent_title] => 'Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device'
[patent_app_type] => utility
[patent_app_number] => 11/196967
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/196967 | Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device | Aug 3, 2005 | Issued |
Array
(
[id] => 847161
[patent_doc_number] => 07384861
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[patent_title] => 'Strain modulation employing process techniques for CMOS technologies'
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[patent_app_number] => 11/183348
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/183348 | Strain modulation employing process techniques for CMOS technologies | Jul 17, 2005 | Issued |
Array
(
[id] => 928517
[patent_doc_number] => 07314827
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[patent_issue_date] => 2008-01-01
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/181908
[patent_app_country] => US
[patent_app_date] => 2005-07-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181908 | Method of manufacturing semiconductor device | Jul 14, 2005 | Issued |
Array
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[id] => 7043330
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[patent_title] => 'Methods of forming assemblies displaying differential negative resistance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181879 | Methods of forming assemblies displaying differential negative resistance | Jul 14, 2005 | Issued |
Array
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[patent_title] => 'Method for forming a lens using sub-micron horizontal tip feature'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/179059 | Method for forming a lens using sub-micron horizontal tip feature | Jul 10, 2005 | Issued |
Array
(
[id] => 861398
[patent_doc_number] => 07372156
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[patent_issue_date] => 2008-05-13
[patent_title] => 'Method to fabricate aligned dual damascene openings'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/174805 | Method to fabricate aligned dual damascene openings | Jul 4, 2005 | Issued |
Array
(
[id] => 856743
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[patent_title] => 'MIM capacitor in a semiconductor device and method therefor'
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Array
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[patent_title] => 'Glass-based semiconductor on insulator structures and methods of making same'
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Array
(
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[patent_title] => 'Method for fabricating an integrated semiconductor circuit and semiconductor circuit'
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Array
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