Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 421865
[patent_doc_number] => 07273796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-25
[patent_title] => 'Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/087218
[patent_app_country] => US
[patent_app_date] => 2005-03-23
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[pdf_file] => patents/07/273/07273796.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087218
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087218 | Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry | Mar 22, 2005 | Issued |
Array
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[patent_issue_date] => 2005-07-28
[patent_title] => 'Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice'
[patent_app_type] => utility
[patent_app_number] => 11/086144
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086144 | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice | Mar 21, 2005 | Issued |
Array
(
[id] => 5760301
[patent_doc_number] => 20060211246
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[patent_kind] => A1
[patent_issue_date] => 2006-09-21
[patent_title] => 'Plasma enhanced atomic layer deposition system and method'
[patent_app_type] => utility
[patent_app_number] => 11/083899
[patent_app_country] => US
[patent_app_date] => 2005-03-21
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[firstpage_image] =>[orig_patent_app_number] => 11083899
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/083899 | Plasma enhanced atomic layer deposition system and method | Mar 20, 2005 | Issued |
Array
(
[id] => 5913053
[patent_doc_number] => 20060128115
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[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Method for forming a shallow trench isolation structure with reduced stress'
[patent_app_type] => utility
[patent_app_number] => 11/076908
[patent_app_country] => US
[patent_app_date] => 2005-03-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/076908 | Method for forming a shallow trench isolation structure with reduced stress | Mar 10, 2005 | Issued |
Array
(
[id] => 5077457
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[patent_issue_date] => 2007-05-31
[patent_title] => 'Semiconductor device'
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[patent_app_number] => 10/583365
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/583365 | Semiconductor device | Mar 8, 2005 | Issued |
Array
(
[id] => 7003731
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[patent_title] => 'Magnetic memory device having magnetic shield layer, and manufacturing method thereof'
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[patent_app_number] => 11/070379
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[firstpage_image] =>[orig_patent_app_number] => 11070379
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Array
(
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[patent_title] => 'Refractory metal nitride barrier layer with gradient nitrogen concentration'
[patent_app_type] => utility
[patent_app_number] => 11/070569
[patent_app_country] => US
[patent_app_date] => 2005-03-02
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[pdf_file] => publications/A1/0156/20050156316.pdf
[firstpage_image] =>[orig_patent_app_number] => 11070569
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/070569 | Refractory metal nitride barrier layer with gradient nitrogen concentration | Mar 1, 2005 | Abandoned |
Array
(
[id] => 5677936
[patent_doc_number] => 20060183292
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[patent_issue_date] => 2006-08-17
[patent_title] => 'STI liner modification method'
[patent_app_type] => utility
[patent_app_number] => 11/059728
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[pdf_file] => publications/A1/0183/20060183292.pdf
[firstpage_image] =>[orig_patent_app_number] => 11059728
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/059728 | STI liner modification method | Feb 16, 2005 | Issued |
Array
(
[id] => 7074904
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[patent_title] => 'Seed layers for metallic interconnects'
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[firstpage_image] =>[orig_patent_app_number] => 11057485
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/057485 | Seed layers for metallic interconnects | Feb 13, 2005 | Issued |
Array
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[patent_title] => 'Semiconductor device and method for fabricating the same'
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[firstpage_image] =>[orig_patent_app_number] => 11040000
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Array
(
[id] => 5874556
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[patent_title] => 'Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits'
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Array
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Array
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[patent_title] => 'Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the implant across the substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/033939 | Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the implant across the substrate | Jan 11, 2005 | Issued |
Array
(
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[patent_title] => 'Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate'
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Array
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Array
(
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[patent_title] => 'Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process'
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Array
(
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[patent_title] => 'Method for forming STI of semiconductor device'
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Array
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