Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 432214
[patent_doc_number] => 07264987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-04
[patent_title] => 'Method of fabricating optoelectronic integrated circuit chip'
[patent_app_type] => utility
[patent_app_number] => 11/012699
[patent_app_country] => US
[patent_app_date] => 2004-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3856
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/264/07264987.pdf
[firstpage_image] =>[orig_patent_app_number] => 11012699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/012699 | Method of fabricating optoelectronic integrated circuit chip | Dec 15, 2004 | Issued |
Array
(
[id] => 6994098
[patent_doc_number] => 20050133874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Method of manufactoring a semiconductor device with trench isolation between two regions having different gate insulating films'
[patent_app_type] => utility
[patent_app_number] => 11/007462
[patent_app_country] => US
[patent_app_date] => 2004-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 56
[patent_no_of_words] => 25777
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20050133874.pdf
[firstpage_image] =>[orig_patent_app_number] => 11007462
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/007462 | Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films | Dec 8, 2004 | Issued |
Array
(
[id] => 654544
[patent_doc_number] => 07109063
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Semiconductor substrate for build-up packages'
[patent_app_type] => utility
[patent_app_number] => 11/003694
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 4024
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/109/07109063.pdf
[firstpage_image] =>[orig_patent_app_number] => 11003694
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/003694 | Semiconductor substrate for build-up packages | Dec 2, 2004 | Issued |
Array
(
[id] => 7252848
[patent_doc_number] => 20050074935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same'
[patent_app_type] => utility
[patent_app_number] => 10/999259
[patent_app_country] => US
[patent_app_date] => 2004-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7686
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20050074935.pdf
[firstpage_image] =>[orig_patent_app_number] => 10999259
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/999259 | Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same | Nov 28, 2004 | Issued |
Array
(
[id] => 5613660
[patent_doc_number] => 20060115588
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'System and method of fabrication and application of thin-films with continuously graded or discrete physical property parameters to functionally broadband monolithic microelectronic optoelectronic/sensor/actuator device arrays'
[patent_app_type] => utility
[patent_app_number] => 10/998149
[patent_app_country] => US
[patent_app_date] => 2004-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6143
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20060115588.pdf
[firstpage_image] =>[orig_patent_app_number] => 10998149
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/998149 | System and method of fabrication and application of thin-films with continuously graded or discrete physical property parameters to functionally broadband monolithic microelectronic optoelectronic/sensor/actuator device arrays | Nov 28, 2004 | Issued |
Array
(
[id] => 686561
[patent_doc_number] => 07078277
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-18
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/996228
[patent_app_country] => US
[patent_app_date] => 2004-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 32
[patent_no_of_words] => 10857
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/078/07078277.pdf
[firstpage_image] =>[orig_patent_app_number] => 10996228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/996228 | Semiconductor device and method for manufacturing the same | Nov 22, 2004 | Issued |
Array
(
[id] => 585153
[patent_doc_number] => 07442621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'Semiconductor process for forming stress absorbent shallow trench isolation structures'
[patent_app_type] => utility
[patent_app_number] => 10/996319
[patent_app_country] => US
[patent_app_date] => 2004-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 3145
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/442/07442621.pdf
[firstpage_image] =>[orig_patent_app_number] => 10996319
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/996319 | Semiconductor process for forming stress absorbent shallow trench isolation structures | Nov 21, 2004 | Issued |
Array
(
[id] => 7005295
[patent_doc_number] => 20050170608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Semiconductor device and, manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/989319
[patent_app_country] => US
[patent_app_date] => 2004-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8244
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20050170608.pdf
[firstpage_image] =>[orig_patent_app_number] => 10989319
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/989319 | Semiconductor device and, manufacturing method thereof | Nov 16, 2004 | Abandoned |
Array
(
[id] => 7097925
[patent_doc_number] => 20050130384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Method for manufacturing resistor of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/988008
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2175
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20050130384.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988008
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988008 | Method for manufacturing resistor of a semiconductor device | Nov 11, 2004 | Abandoned |
Array
(
[id] => 52925
[patent_doc_number] => 07772052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-10
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/983584
[patent_app_country] => US
[patent_app_date] => 2004-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 32
[patent_no_of_words] => 11751
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/772/07772052.pdf
[firstpage_image] =>[orig_patent_app_number] => 10983584
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/983584 | Method of manufacturing semiconductor device | Nov 8, 2004 | Issued |
Array
(
[id] => 7104121
[patent_doc_number] => 20050106847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Method of manufacturing semiconductor device and method of treating semiconductor surface'
[patent_app_type] => utility
[patent_app_number] => 10/983243
[patent_app_country] => US
[patent_app_date] => 2004-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5060
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20050106847.pdf
[firstpage_image] =>[orig_patent_app_number] => 10983243
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/983243 | Method of manufacturing semiconductor device and method of treating semiconductor surface | Nov 7, 2004 | Issued |
Array
(
[id] => 6918178
[patent_doc_number] => 20050095739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Process for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/984532
[patent_app_country] => US
[patent_app_date] => 2004-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1958
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20050095739.pdf
[firstpage_image] =>[orig_patent_app_number] => 10984532
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/984532 | Process for manufacturing semiconductor device | Nov 7, 2004 | Issued |
Array
(
[id] => 7010891
[patent_doc_number] => 20050064607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Magnetically shielded circuit board'
[patent_app_type] => utility
[patent_app_number] => 10/980178
[patent_app_country] => US
[patent_app_date] => 2004-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3753
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20050064607.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980178
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980178 | Magnetically shielded circuit board | Nov 3, 2004 | Issued |
Array
(
[id] => 6991049
[patent_doc_number] => 20050090086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Method of fabricating self-aligned contact structures'
[patent_app_type] => utility
[patent_app_number] => 10/972368
[patent_app_country] => US
[patent_app_date] => 2004-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1419
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20050090086.pdf
[firstpage_image] =>[orig_patent_app_number] => 10972368
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/972368 | Method of fabricating self-aligned contact structures | Oct 25, 2004 | Issued |
Array
(
[id] => 6988680
[patent_doc_number] => 20050087802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Semiconductor devices having dual spacers and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/971984
[patent_app_country] => US
[patent_app_date] => 2004-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2689
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20050087802.pdf
[firstpage_image] =>[orig_patent_app_number] => 10971984
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/971984 | Semiconductor devices having dual spacers and methods of fabricating the same | Oct 21, 2004 | Issued |
Array
(
[id] => 785230
[patent_doc_number] => 06989317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-01-24
[patent_title] => 'Trench formation in semiconductor integrated circuits (ICs)'
[patent_app_type] => utility
[patent_app_number] => 10/904088
[patent_app_country] => US
[patent_app_date] => 2004-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 3283
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/989/06989317.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904088
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904088 | Trench formation in semiconductor integrated circuits (ICs) | Oct 21, 2004 | Issued |
Array
(
[id] => 7253069
[patent_doc_number] => 20050074987
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/968093
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 22578
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20050074987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968093
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968093 | Method of manufacturing semiconductor device | Oct 19, 2004 | Issued |
Array
(
[id] => 7154437
[patent_doc_number] => 20050082625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers'
[patent_app_type] => utility
[patent_app_number] => 10/969564
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6728
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20050082625.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969564
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969564 | Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers | Oct 19, 2004 | Issued |
Array
(
[id] => 7008417
[patent_doc_number] => 20050062133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Structure and method for eliminating metal contact to P-well of N-well shorts or high leakage paths using polysilicon liner'
[patent_app_type] => utility
[patent_app_number] => 10/969705
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2839
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0062/20050062133.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969705
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969705 | Structure and method for eliminating metal contact to P-well of N-well shorts or high leakage paths using polysilicon liner | Oct 19, 2004 | Abandoned |
Array
(
[id] => 7081872
[patent_doc_number] => 20050047252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Rare earth metal oxide memory element based on charge storage and method for manufacturing same'
[patent_app_type] => utility
[patent_app_number] => 10/954275
[patent_app_country] => US
[patent_app_date] => 2004-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2517
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20050047252.pdf
[firstpage_image] =>[orig_patent_app_number] => 10954275
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/954275 | Rare earth metal oxide memory element based on charge storage and method for manufacturing same | Sep 30, 2004 | Issued |