Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 432266 [patent_doc_number] => 07265039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Method for fabricating semiconductor device with improved refresh time' [patent_app_type] => utility [patent_app_number] => 10/750318 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3735 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265039.pdf [firstpage_image] =>[orig_patent_app_number] => 10750318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/750318
Method for fabricating semiconductor device with improved refresh time Dec 29, 2003 Issued
Array ( [id] => 7429467 [patent_doc_number] => 20040266103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method for fabricating capacitor using metastable-polysilicon process' [patent_app_type] => new [patent_app_number] => 10/744048 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4072 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266103.pdf [firstpage_image] =>[orig_patent_app_number] => 10744048 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744048
Method for fabricating capacitor using metastable-polysilicon process Dec 23, 2003 Issued
Array ( [id] => 7234992 [patent_doc_number] => 20040157364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Manufacturing method of a microelectromechanical switch' [patent_app_type] => new [patent_app_number] => 10/746868 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5209 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157364.pdf [firstpage_image] =>[orig_patent_app_number] => 10746868 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746868
Manufacturing method of a microelectromechanical switch Dec 23, 2003 Issued
Array ( [id] => 5667144 [patent_doc_number] => 20060172494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Method for the production of a semiconductor component' [patent_app_type] => utility [patent_app_number] => 10/541819 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20060172494.pdf [firstpage_image] =>[orig_patent_app_number] => 10541819 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/541819
Method for the production of a semiconductor component Dec 22, 2003 Issued
Array ( [id] => 7287285 [patent_doc_number] => 20040147085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Method for fabricating a capacitor using a metal insulator metal structure' [patent_app_type] => new [patent_app_number] => 10/743573 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147085.pdf [firstpage_image] =>[orig_patent_app_number] => 10743573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743573
Method for fabricating a capacitor using a metal insulator metal structure Dec 21, 2003 Issued
Array ( [id] => 7083311 [patent_doc_number] => 20050048691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'High temperature attachment of organic molecules to substrates' [patent_app_type] => utility [patent_app_number] => 10/742596 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16222 [patent_no_of_claims] => 105 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20050048691.pdf [firstpage_image] =>[orig_patent_app_number] => 10742596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742596
High temperature attachment of organic molecules to substrates Dec 18, 2003 Issued
Array ( [id] => 6994005 [patent_doc_number] => 20050133781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Multilayer device and method of making' [patent_app_type] => utility [patent_app_number] => 10/739298 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5857 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133781.pdf [firstpage_image] =>[orig_patent_app_number] => 10739298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739298
Multilayer device and method of making Dec 18, 2003 Issued
Array ( [id] => 7309258 [patent_doc_number] => 20040142535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Method for forming metal-insulator-metal capacitor of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/738398 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1658 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142535.pdf [firstpage_image] =>[orig_patent_app_number] => 10738398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/738398
Method for forming metal-insulator-metal capacitor of semiconductor device Dec 16, 2003 Abandoned
Array ( [id] => 7283667 [patent_doc_number] => 20040145058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Buried connections in an integrated circuit substrate' [patent_app_type] => new [patent_app_number] => 10/735518 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3451 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145058.pdf [firstpage_image] =>[orig_patent_app_number] => 10735518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735518
Buried connections in an integrated circuit substrate Dec 11, 2003 Abandoned
Array ( [id] => 7471612 [patent_doc_number] => 20040121571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/732518 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 15452 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121571.pdf [firstpage_image] =>[orig_patent_app_number] => 10732518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732518
Method of manufacturing a semiconductor device having a multi-layered wiring structure Dec 10, 2003 Issued
Array ( [id] => 544243 [patent_doc_number] => 07163896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'Biased H2 etch process in deposition-etch-deposition gap fill' [patent_app_type] => utility [patent_app_number] => 10/733858 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/163/07163896.pdf [firstpage_image] =>[orig_patent_app_number] => 10733858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733858
Biased H2 etch process in deposition-etch-deposition gap fill Dec 9, 2003 Issued
Array ( [id] => 931095 [patent_doc_number] => 06979599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Chip with molded cap array' [patent_app_type] => utility [patent_app_number] => 10/728798 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 5107 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979599.pdf [firstpage_image] =>[orig_patent_app_number] => 10728798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728798
Chip with molded cap array Dec 7, 2003 Issued
Array ( [id] => 996548 [patent_doc_number] => 06913987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Method for fabricating self-aligned contact connections on buried bit lines' [patent_app_type] => utility [patent_app_number] => 10/728388 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2303 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/913/06913987.pdf [firstpage_image] =>[orig_patent_app_number] => 10728388 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728388
Method for fabricating self-aligned contact connections on buried bit lines Dec 4, 2003 Issued
Array ( [id] => 7429809 [patent_doc_number] => 20040266149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/727478 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1935 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266149.pdf [firstpage_image] =>[orig_patent_app_number] => 10727478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/727478
Method of manufacturing semiconductor device Dec 3, 2003 Issued
Array ( [id] => 708751 [patent_doc_number] => 07061098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Electronic component and method for its production' [patent_app_type] => utility [patent_app_number] => 10/723998 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3910 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061098.pdf [firstpage_image] =>[orig_patent_app_number] => 10723998 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/723998
Electronic component and method for its production Nov 25, 2003 Issued
Array ( [id] => 7104109 [patent_doc_number] => 20050106835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Trench isolation structure and method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 10/716278 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106835.pdf [firstpage_image] =>[orig_patent_app_number] => 10716278 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716278
Trench isolation structure and method of manufacture therefor Nov 17, 2003 Abandoned
Array ( [id] => 1031036 [patent_doc_number] => 06878587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Method and structure for reducing contact aspect ratios' [patent_app_type] => utility [patent_app_number] => 10/714688 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4971 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878587.pdf [firstpage_image] =>[orig_patent_app_number] => 10714688 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714688
Method and structure for reducing contact aspect ratios Nov 16, 2003 Issued
Array ( [id] => 558906 [patent_doc_number] => 07468535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Self-aligned integrated electronic devices' [patent_app_type] => utility [patent_app_number] => 10/713538 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2860 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/468/07468535.pdf [firstpage_image] =>[orig_patent_app_number] => 10713538 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713538
Self-aligned integrated electronic devices Nov 13, 2003 Issued
Array ( [id] => 7324336 [patent_doc_number] => 20040137752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Semiconductor wafer treatment method, semiconductor wafer inspection method, semiconductor device development method and semiconductor wafer treatment apparatus' [patent_app_type] => new [patent_app_number] => 10/706090 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8635 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137752.pdf [firstpage_image] =>[orig_patent_app_number] => 10706090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706090
Semiconductor wafer treatment method, semiconductor wafer inspection method, semiconductor device development method and semiconductor wafer treatment apparatus Nov 12, 2003 Issued
Array ( [id] => 650886 [patent_doc_number] => 07112463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Method for making devices using ink jet printing' [patent_app_type] => utility [patent_app_number] => 10/713329 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112463.pdf [firstpage_image] =>[orig_patent_app_number] => 10713329 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713329
Method for making devices using ink jet printing Nov 12, 2003 Issued
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