Christopher E Dunay

Array ( [id] => 1037904 [patent_doc_number] => 06873056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Electrode-to-electrode bond structure' [patent_app_type] => utility [patent_app_number] => 10/704553 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 31 [patent_no_of_words] => 15344 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873056.pdf [firstpage_image] =>[orig_patent_app_number] => 10704553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 662947 [patent_doc_number] => 07101801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method of manufacturing semiconductor device using chemical mechanical polishing' [patent_app_type] => utility [patent_app_number] => 10/704628 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101801.pdf [firstpage_image] =>[orig_patent_app_number] => 10704628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1037511 [patent_doc_number] => 06872660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Methods of forming conductive contacts' [patent_app_type] => utility [patent_app_number] => 10/703778 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2637 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872660.pdf [firstpage_image] =>[orig_patent_app_number] => 10703778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1085598 [patent_doc_number] => 06830943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Thin film CMOS calibration standard having protective cover layer' [patent_app_type] => B1 [patent_app_number] => 10/702165 [patent_app_country] => US [patent_app_date] => 2003-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3898 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/830/06830943.pdf [firstpage_image] =>[orig_patent_app_number] => 10702165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7365195 [patent_doc_number] => 20040092084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Method for treating a semiconductor material for subsequent bonding' [patent_app_type] => new [patent_app_number] => 10/695938 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5080 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092084.pdf [firstpage_image] =>[orig_patent_app_number] => 10695938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1110918 [patent_doc_number] => 06806141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Field effect transistor with gate layer and method of making same' [patent_app_type] => B2 [patent_app_number] => 10/696838 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 25 [patent_no_of_words] => 4768 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806141.pdf [firstpage_image] =>[orig_patent_app_number] => 10696838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7189839 [patent_doc_number] => 20040084751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Inductive storage capacitor' [patent_app_type] => new [patent_app_number] => 10/694661 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9697 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20040084751.pdf [firstpage_image] =>[orig_patent_app_number] => 10694661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7287232 [patent_doc_number] => 20040147067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Semiconductor apparatus and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/690840 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7402 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147067.pdf [firstpage_image] =>[orig_patent_app_number] => 10690840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 944102 [patent_doc_number] => 06967156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Method to fabricate aligned dual damascene openings' [patent_app_type] => utility [patent_app_number] => 10/690998 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2072 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967156.pdf [firstpage_image] =>[orig_patent_app_number] => 10690998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7304930 [patent_doc_number] => 20040115891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Process and installation for doping an etched pattern of resistive elements' [patent_app_type] => new [patent_app_number] => 10/689528 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3528 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115891.pdf [firstpage_image] =>[orig_patent_app_number] => 10689528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 759181 [patent_doc_number] => 07015527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Metal oxynitride capacitor barrier layer' [patent_app_type] => utility [patent_app_number] => 10/688678 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7812 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015527.pdf [firstpage_image] =>[orig_patent_app_number] => 10688678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 557366 [patent_doc_number] => 07157352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Method for producing ultra-thin semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/680548 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 47 [patent_no_of_words] => 23507 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157352.pdf [firstpage_image] =>[orig_patent_app_number] => 10680548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 988126 [patent_doc_number] => 06921681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Process for manufacturing photosensitive module' [patent_app_type] => utility [patent_app_number] => 10/681458 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1959 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921681.pdf [firstpage_image] =>[orig_patent_app_number] => 10681458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 931141 [patent_doc_number] => 06979645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method of producing a semiconductor device having copper wiring' [patent_app_type] => utility [patent_app_number] => 10/680668 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6741 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979645.pdf [firstpage_image] =>[orig_patent_app_number] => 10680668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134141 [patent_doc_number] => 06784052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method of forming a capacitor with two diffusion barrier layers formed in the same step' [patent_app_type] => B2 [patent_app_number] => 10/676498 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3947 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784052.pdf [firstpage_image] =>[orig_patent_app_number] => 10676498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 677117 [patent_doc_number] => 07087977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Semiconductor device including multiple wiring layers and circuits operating in different frequency bands' [patent_app_type] => utility [patent_app_number] => 10/670258 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 58 [patent_no_of_words] => 21843 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087977.pdf [firstpage_image] =>[orig_patent_app_number] => 10670258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 542452 [patent_doc_number] => 07169713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Atomic layer deposition (ALD) method with enhanced deposition rate' [patent_app_type] => utility [patent_app_number] => 10/672778 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2496 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/169/07169713.pdf [firstpage_image] =>[orig_patent_app_number] => 10672778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7116747 [patent_doc_number] => 20050070048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Devices and methods employing high thermal conductivity heat dissipation substrates' [patent_app_type] => utility [patent_app_number] => 10/672968 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4324 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070048.pdf [firstpage_image] =>[orig_patent_app_number] => 10672968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7008350 [patent_doc_number] => 20050062066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Semiconductor devices having regions of induced high and low conductivity, and methods of making the same' [patent_app_type] => utility [patent_app_number] => 10/671303 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15786 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062066.pdf [firstpage_image] =>[orig_patent_app_number] => 10671303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7010920 [patent_doc_number] => 20050064636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method and apparatus for fabricating CMOS field effect transistors' [patent_app_type] => utility [patent_app_number] => 10/669898 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2810 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064636.pdf [firstpage_image] =>[orig_patent_app_number] => 10669898 [rel_patent_id] =>[rel_patent_doc_number] =>)