Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 782731 [patent_doc_number] => 06991979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs' [patent_app_type] => utility [patent_app_number] => 10/605311 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 3753 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/991/06991979.pdf [firstpage_image] =>[orig_patent_app_number] => 10605311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605311
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs Sep 21, 2003 Issued
Array ( [id] => 7609841 [patent_doc_number] => 06998347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method of reworking layers over substrate' [patent_app_type] => utility [patent_app_number] => 10/605238 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1019 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998347.pdf [firstpage_image] =>[orig_patent_app_number] => 10605238 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605238
Method of reworking layers over substrate Sep 16, 2003 Issued
Array ( [id] => 1050010 [patent_doc_number] => 06861287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Multiple chip stack structure and cooling system' [patent_app_type] => utility [patent_app_number] => 10/662828 [patent_app_country] => US [patent_app_date] => 2003-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6692 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861287.pdf [firstpage_image] =>[orig_patent_app_number] => 10662828 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/662828
Multiple chip stack structure and cooling system Sep 14, 2003 Issued
Array ( [id] => 7383704 [patent_doc_number] => 20040082198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/659748 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4550 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082198.pdf [firstpage_image] =>[orig_patent_app_number] => 10659748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659748
Method of manufacturing semiconductor device Sep 10, 2003 Abandoned
Array ( [id] => 7235155 [patent_doc_number] => 20040157389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Semiconductor memory cell and method for fabricating the memory cell' [patent_app_type] => new [patent_app_number] => 10/657928 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5575 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157389.pdf [firstpage_image] =>[orig_patent_app_number] => 10657928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657928
Semiconductor memory cell and method for fabricating the memory cell Sep 9, 2003 Issued
Array ( [id] => 7383627 [patent_doc_number] => 20040082188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Electronic assembly with high capacity thermal interface and methods of manufacture' [patent_app_type] => new [patent_app_number] => 10/655728 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6474 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082188.pdf [firstpage_image] =>[orig_patent_app_number] => 10655728 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/655728
Electronic assembly with high capacity thermal interface and methods of manufacture Sep 4, 2003 Issued
Array ( [id] => 931143 [patent_doc_number] => 06979647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method for chemical etch control of noble metals in the presence of less noble metals' [patent_app_type] => utility [patent_app_number] => 10/653548 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3798 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979647.pdf [firstpage_image] =>[orig_patent_app_number] => 10653548 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653548
Method for chemical etch control of noble metals in the presence of less noble metals Sep 1, 2003 Issued
Array ( [id] => 7365133 [patent_doc_number] => 20040092061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/648288 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20841 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092061.pdf [firstpage_image] =>[orig_patent_app_number] => 10648288 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648288
Method for manufacturing a semiconductor device using laser light Aug 26, 2003 Issued
Array ( [id] => 1068689 [patent_doc_number] => 06844215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Method of forming tapered drain-to-anode connectors in a back plane for an active matrix OLED device' [patent_app_type] => utility [patent_app_number] => 10/647398 [patent_app_country] => US [patent_app_date] => 2003-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5488 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844215.pdf [firstpage_image] =>[orig_patent_app_number] => 10647398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/647398
Method of forming tapered drain-to-anode connectors in a back plane for an active matrix OLED device Aug 24, 2003 Issued
Array ( [id] => 5732961 [patent_doc_number] => 20060258078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Atomic layer deposition of high-k metal oxides' [patent_app_type] => utility [patent_app_number] => 10/524814 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2761 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258078.pdf [firstpage_image] =>[orig_patent_app_number] => 10524814 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/524814
Atomic layer deposition of high-k metal oxides Aug 17, 2003 Abandoned
Array ( [id] => 734271 [patent_doc_number] => 07038309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Chip package structure with glass substrate' [patent_app_type] => utility [patent_app_number] => 10/643788 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038309.pdf [firstpage_image] =>[orig_patent_app_number] => 10643788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/643788
Chip package structure with glass substrate Aug 14, 2003 Issued
Array ( [id] => 1059521 [patent_doc_number] => 06852611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'ROM embedded DRAM with dielectric removal/short' [patent_app_type] => utility [patent_app_number] => 10/631918 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 7185 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852611.pdf [firstpage_image] =>[orig_patent_app_number] => 10631918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631918
ROM embedded DRAM with dielectric removal/short Jul 30, 2003 Issued
Array ( [id] => 7471339 [patent_doc_number] => 20040121519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method of balanced coefficient of thermal expansion for flip chip ball grid array' [patent_app_type] => new [patent_app_number] => 10/631328 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2667 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121519.pdf [firstpage_image] =>[orig_patent_app_number] => 10631328 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631328
Method of balanced coefficient of thermal expansion for flip chip ball grid array Jul 29, 2003 Issued
Array ( [id] => 7304978 [patent_doc_number] => 20040115916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Selective placement of dislocation arrays' [patent_app_type] => new [patent_app_number] => 10/629498 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12471 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115916.pdf [firstpage_image] =>[orig_patent_app_number] => 10629498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629498
Selective placement of dislocation arrays Jul 28, 2003 Abandoned
Array ( [id] => 1095962 [patent_doc_number] => 06821850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of manufacturing a multi-level flash EEPROM cell' [patent_app_type] => B2 [patent_app_number] => 10/627917 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1658 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821850.pdf [firstpage_image] =>[orig_patent_app_number] => 10627917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627917
Method of manufacturing a multi-level flash EEPROM cell Jul 27, 2003 Issued
Array ( [id] => 7069701 [patent_doc_number] => 20050245086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Adaptive electropolishing using thickness measurement and removal of barrier and sacrificial layers' [patent_app_type] => utility [patent_app_number] => 10/520493 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5745 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20050245086.pdf [firstpage_image] =>[orig_patent_app_number] => 10520493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/520493
Adaptive electropolishing using thickness measurement and removal of barrier and sacrificial layers Jul 21, 2003 Abandoned
Array ( [id] => 721282 [patent_doc_number] => 07049682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Multi-chip semiconductor package with integral shield and antenna' [patent_app_type] => utility [patent_app_number] => 10/621780 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9219 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049682.pdf [firstpage_image] =>[orig_patent_app_number] => 10621780 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621780
Multi-chip semiconductor package with integral shield and antenna Jul 15, 2003 Issued
Array ( [id] => 1068722 [patent_doc_number] => 06844248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Method of doping silicon, metal doped silicon, method of making solar cells, and solar cells' [patent_app_type] => utility [patent_app_number] => 10/617698 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4295 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844248.pdf [firstpage_image] =>[orig_patent_app_number] => 10617698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617698
Method of doping silicon, metal doped silicon, method of making solar cells, and solar cells Jul 13, 2003 Issued
Array ( [id] => 7121728 [patent_doc_number] => 20050013557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Optical packages and methods for controlling a standoff height in optical packages' [patent_app_type] => utility [patent_app_number] => 10/619348 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2069 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013557.pdf [firstpage_image] =>[orig_patent_app_number] => 10619348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619348
Optical packages and methods for controlling a standoff height in optical packages Jul 13, 2003 Abandoned
Array ( [id] => 7130173 [patent_doc_number] => 20040041202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Non-volatile memory device having dummy pattern' [patent_app_type] => new [patent_app_number] => 10/619998 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3761 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041202.pdf [firstpage_image] =>[orig_patent_app_number] => 10619998 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619998
Non-volatile memory device having dummy pattern Jul 13, 2003 Issued
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