Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7313616
[patent_doc_number] => 20040033664
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-19
[patent_title] => 'Semiconductor device having electrically erasable programmable read-only memory (EEPROM) and Mask-ROM and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/440238
[patent_app_country] => US
[patent_app_date] => 2003-05-19
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20040033664.pdf
[firstpage_image] =>[orig_patent_app_number] => 10440238
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/440238 | Semiconductor device having electrically erasable programmable read-only memory (EEPROM) and mask-ROM and method of fabricating the same | May 18, 2003 | Issued |
Array
(
[id] => 7423795
[patent_doc_number] => 20040229460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Surface treatment of metal interconnect lines'
[patent_app_type] => new
[patent_app_number] => 10/439358
[patent_app_country] => US
[patent_app_date] => 2003-05-16
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[pdf_file] => publications/A1/0229/20040229460.pdf
[firstpage_image] =>[orig_patent_app_number] => 10439358
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/439358 | Surface treatment of metal interconnect lines | May 15, 2003 | Issued |
Array
(
[id] => 938416
[patent_doc_number] => 06972245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-06
[patent_title] => 'Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures'
[patent_app_type] => utility
[patent_app_number] => 10/439748
[patent_app_country] => US
[patent_app_date] => 2003-05-15
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[pdf_file] => patents/06/972/06972245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10439748
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/439748 | Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures | May 14, 2003 | Issued |
Array
(
[id] => 6807253
[patent_doc_number] => 20030197192
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Display device with color filter covering portion of reflecting part'
[patent_app_type] => new
[patent_app_number] => 10/436870
[patent_app_country] => US
[patent_app_date] => 2003-05-13
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0197/20030197192.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/436870 | Display device with color filter covering portion of reflecting part | May 12, 2003 | Issued |
Array
(
[id] => 6725197
[patent_doc_number] => 20030207509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-06
[patent_title] => 'Semiconductor integrated circuit device and manufacture method therefore'
[patent_app_type] => new
[patent_app_number] => 10/435956
[patent_app_country] => US
[patent_app_date] => 2003-05-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0207/20030207509.pdf
[firstpage_image] =>[orig_patent_app_number] => 10435956
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/435956 | Semiconductor integrated circuit device and manufacture method therefore | May 11, 2003 | Abandoned |
Array
(
[id] => 1031502
[patent_doc_number] => 06879034
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-12
[patent_title] => 'Semiconductor package including low temperature co-fired ceramic substrate'
[patent_app_type] => utility
[patent_app_number] => 10/427118
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[patent_app_date] => 2003-05-01
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[pdf_file] => patents/06/879/06879034.pdf
[firstpage_image] =>[orig_patent_app_number] => 10427118
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/427118 | Semiconductor package including low temperature co-fired ceramic substrate | Apr 30, 2003 | Issued |
Array
(
[id] => 565549
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[patent_issue_date] => 2008-12-16
[patent_title] => 'Graded/stepped silicide process to improve MOS transistor'
[patent_app_type] => utility
[patent_app_number] => 10/424800
[patent_app_country] => US
[patent_app_date] => 2003-04-28
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[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/07/465/07465660.pdf
[firstpage_image] =>[orig_patent_app_number] => 10424800
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/424800 | Graded/stepped silicide process to improve MOS transistor | Apr 27, 2003 | Issued |
Array
(
[id] => 645249
[patent_doc_number] => 07118988
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'Vertically wired integrated circuit and method of fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/424022
[patent_app_country] => US
[patent_app_date] => 2003-04-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/118/07118988.pdf
[firstpage_image] =>[orig_patent_app_number] => 10424022
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/424022 | Vertically wired integrated circuit and method of fabrication | Apr 24, 2003 | Issued |
Array
(
[id] => 1120816
[patent_doc_number] => 06798004
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-28
[patent_title] => 'Magnetoresistive random access memory devices and methods for fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 10/421095
[patent_app_country] => US
[patent_app_date] => 2003-04-22
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[pdf_file] => patents/06/798/06798004.pdf
[firstpage_image] =>[orig_patent_app_number] => 10421095
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/421095 | Magnetoresistive random access memory devices and methods for fabricating the same | Apr 21, 2003 | Issued |
Array
(
[id] => 1128163
[patent_doc_number] => 06791113
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-14
[patent_title] => 'Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer'
[patent_app_type] => B2
[patent_app_number] => 10/414610
[patent_app_country] => US
[patent_app_date] => 2003-04-15
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[pdf_file] => patents/06/791/06791113.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/414610 | Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer | Apr 14, 2003 | Issued |
Array
(
[id] => 6827581
[patent_doc_number] => 20030178639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Inductive storage capacitor'
[patent_app_type] => new
[patent_app_number] => 10/413795
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[firstpage_image] =>[orig_patent_app_number] => 10413795
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/413795 | Inductive storage capacitor | Apr 13, 2003 | Abandoned |
Array
(
[id] => 1163593
[patent_doc_number] => 06759341
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-06
[patent_title] => 'Wafering method comprising a plasma etch with a gas emitting wafer holder'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412978 | Wafering method comprising a plasma etch with a gas emitting wafer holder | Apr 8, 2003 | Issued |
Array
(
[id] => 613156
[patent_doc_number] => 07148555
[patent_country] => US
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[patent_title] => 'Method for enhancing electrode surface area in DRAM cell capacitors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/408358 | Method for enhancing electrode surface area in DRAM cell capacitors | Apr 6, 2003 | Issued |
Array
(
[id] => 7399017
[patent_doc_number] => 20040018724
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[patent_title] => 'Plating method'
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Array
(
[id] => 6740380
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[patent_title] => 'Electronic component, manufacturing method therefor, aggregate electronic component, mounting structure of electronic component, and electronic device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/400026 | Method for making a mounting structure for an electronic component having an external terminal electrode | Mar 25, 2003 | Issued |
Array
(
[id] => 6829987
[patent_doc_number] => 20030181045
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[patent_title] => 'Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/396902 | Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film | Mar 24, 2003 | Issued |
Array
(
[id] => 7343996
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[patent_issue_date] => 2004-09-30
[patent_title] => 'WIRE BONDING FOR THIN SEMICONDUCTOR PACKAGE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395584 | Wire bonding for thin semiconductor package | Mar 23, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/391005 | Semiconductor package with a thermoset bond | Mar 17, 2003 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/379470 | Atomic layer deposited dielectric layers | Mar 3, 2003 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 10371515
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/371515 | Single unit automated assembly of flex enhanced ball grid array packages | Feb 19, 2003 | Issued |