Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6801313 [patent_doc_number] => 20030096478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Lateral bipolar transistor and method for producing the same' [patent_app_type] => new [patent_app_number] => 10/300440 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12184 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096478.pdf [firstpage_image] =>[orig_patent_app_number] => 10300440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300440
Lateral bipolar transistor Nov 19, 2002 Issued
Array ( [id] => 7362610 [patent_doc_number] => 20040091625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Methods of filling a feature on a substrate with copper nanocrystals' [patent_app_type] => new [patent_app_number] => 10/290498 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10431 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20040091625.pdf [firstpage_image] =>[orig_patent_app_number] => 10290498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290498
Methods of filling a feature on a substrate with copper nanocrystals Nov 7, 2002 Issued
Array ( [id] => 1146655 [patent_doc_number] => 06774033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Metal stack for local interconnect layer' [patent_app_type] => B1 [patent_app_number] => 10/287258 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2655 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774033.pdf [firstpage_image] =>[orig_patent_app_number] => 10287258 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287258
Metal stack for local interconnect layer Nov 3, 2002 Issued
Array ( [id] => 959031 [patent_doc_number] => 06953977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Micromechanical piezoelectric device' [patent_app_type] => utility [patent_app_number] => 10/284048 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 6515 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/953/06953977.pdf [firstpage_image] =>[orig_patent_app_number] => 10284048 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/284048
Micromechanical piezoelectric device Oct 28, 2002 Issued
Array ( [id] => 6696908 [patent_doc_number] => 20030109102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method of manufacturing semiconductor device and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/278918 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 15787 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109102.pdf [firstpage_image] =>[orig_patent_app_number] => 10278918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278918
Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors Oct 23, 2002 Issued
Array ( [id] => 6750591 [patent_doc_number] => 20030045111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Methods of etching a contact opening over a node location on a semiconductor substrate' [patent_app_type] => new [patent_app_number] => 10/278530 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4125 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045111.pdf [firstpage_image] =>[orig_patent_app_number] => 10278530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278530
Methods of etching a contact opening over a node location on a semiconductor substrate Oct 21, 2002 Issued
Array ( [id] => 6690881 [patent_doc_number] => 20030038313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/271529 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038313.pdf [firstpage_image] =>[orig_patent_app_number] => 10271529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271529
Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same Oct 16, 2002 Issued
Array ( [id] => 7204834 [patent_doc_number] => 20040070021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Flash memory array with increased coupling between floating and control gates' [patent_app_type] => new [patent_app_number] => 10/268635 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7068 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20040070021.pdf [firstpage_image] =>[orig_patent_app_number] => 10268635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268635
Flash memory array with increased coupling between floating and control gates Oct 8, 2002 Issued
Array ( [id] => 6690908 [patent_doc_number] => 20030038340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same' [patent_app_type] => new [patent_app_number] => 10/264950 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6685 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038340.pdf [firstpage_image] =>[orig_patent_app_number] => 10264950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/264950
Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same Oct 3, 2002 Issued
Array ( [id] => 7348885 [patent_doc_number] => 20040248340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Process for large-scale production of cdte/cds thin film solar cells' [patent_app_type] => new [patent_app_number] => 10/491938 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20040248340.pdf [firstpage_image] =>[orig_patent_app_number] => 10491938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/491938
Process for large-scale production of CdTe/CdS thin film solar cells Oct 3, 2002 Issued
Array ( [id] => 1183156 [patent_doc_number] => 06737726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Resistance variable device, analog memory device, and programmable memory cell' [patent_app_type] => B2 [patent_app_number] => 10/264677 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2816 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737726.pdf [firstpage_image] =>[orig_patent_app_number] => 10264677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/264677
Resistance variable device, analog memory device, and programmable memory cell Oct 2, 2002 Issued
Array ( [id] => 7268964 [patent_doc_number] => 20040057482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'GaN structures having low dislocation density and methods of manufacture' [patent_app_type] => new [patent_app_number] => 10/255181 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3350 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20040057482.pdf [firstpage_image] =>[orig_patent_app_number] => 10255181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255181
GaN structures having low dislocation density and methods of manufacture Sep 24, 2002 Issued
Array ( [id] => 623556 [patent_doc_number] => 07138306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Laser irradiation method and laser irradiation device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/252828 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 60 [patent_no_of_words] => 18591 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138306.pdf [firstpage_image] =>[orig_patent_app_number] => 10252828 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252828
Laser irradiation method and laser irradiation device and method of manufacturing semiconductor device Sep 23, 2002 Issued
Array ( [id] => 7025635 [patent_doc_number] => 20050020029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Method of producing a contact system on the rear of a component with stacked substrates and a component equipped with one such contact system' [patent_app_type] => utility [patent_app_number] => 10/490468 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3232 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20050020029.pdf [firstpage_image] =>[orig_patent_app_number] => 10490468 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/490468
Method of producing a contact system on the rear of a component with stacked substrates Sep 19, 2002 Issued
Array ( [id] => 1116850 [patent_doc_number] => 06800872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Active matrix thin film transistor' [patent_app_type] => B2 [patent_app_number] => 10/235493 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 207 [patent_no_of_words] => 14485 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800872.pdf [firstpage_image] =>[orig_patent_app_number] => 10235493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/235493
Active matrix thin film transistor Sep 5, 2002 Issued
Array ( [id] => 6316947 [patent_doc_number] => 20020195650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Semiconductor memory device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/233798 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2175 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20020195650.pdf [firstpage_image] =>[orig_patent_app_number] => 10233798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233798
Method of making a flash memory device with an inverted tapered floating gate Sep 2, 2002 Issued
Array ( [id] => 741052 [patent_doc_number] => 07030010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures' [patent_app_type] => utility [patent_app_number] => 10/230678 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4061 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030010.pdf [firstpage_image] =>[orig_patent_app_number] => 10230678 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230678
Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures Aug 28, 2002 Issued
Array ( [id] => 7131782 [patent_doc_number] => 20040042265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method and apparatus for controlling metal doping of a chalcogenide memory element' [patent_app_type] => new [patent_app_number] => 10/230189 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4515 [patent_no_of_claims] => 110 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042265.pdf [firstpage_image] =>[orig_patent_app_number] => 10230189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230189
Method of forming a resistance variable memory element Aug 28, 2002 Issued
Array ( [id] => 7629893 [patent_doc_number] => 06818462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED' [patent_app_type] => B1 [patent_app_number] => 10/224028 [patent_app_country] => US [patent_app_date] => 2002-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2541 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818462.pdf [firstpage_image] =>[orig_patent_app_number] => 10224028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224028
METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED Aug 18, 2002 Issued
10/223446 Vertically wired intgrated circuit and method of fabrication Aug 18, 2002 Abandoned
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