Christopher E Dunay

Array ( [id] => 6787769 [patent_doc_number] => 20030139008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/216358 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4264 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139008.pdf [firstpage_image] =>[orig_patent_app_number] => 10216358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7383698 [patent_doc_number] => 20040029377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Refractory metal nitride barrier layer with gradient nitrogen concentration' [patent_app_type] => new [patent_app_number] => 10/214638 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029377.pdf [firstpage_image] =>[orig_patent_app_number] => 10214638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1205718 [patent_doc_number] => 06716753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method for forming a self-passivated copper interconnect structure' [patent_app_type] => B1 [patent_app_number] => 10/207548 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2230 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716753.pdf [firstpage_image] =>[orig_patent_app_number] => 10207548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6781118 [patent_doc_number] => 20030062565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Semiconductor device and method of fabricating same' [patent_app_type] => new [patent_app_number] => 10/202500 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9592 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062565.pdf [firstpage_image] =>[orig_patent_app_number] => 10202500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6730366 [patent_doc_number] => 20030186556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'METHODS USED IN FABRICATING GATES IN INTEGRATED CIRCUIT DEVICE STRUCTURES' [patent_app_type] => new [patent_app_number] => 10/198298 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4032 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186556.pdf [firstpage_image] =>[orig_patent_app_number] => 10198298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1310980 [patent_doc_number] => 06613690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers' [patent_app_type] => B1 [patent_app_number] => 10/197318 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2763 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613690.pdf [firstpage_image] =>[orig_patent_app_number] => 10197318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6730368 [patent_doc_number] => 20030186558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Planarization for integrated circuits' [patent_app_type] => new [patent_app_number] => 10/195678 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1057 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186558.pdf [firstpage_image] =>[orig_patent_app_number] => 10195678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1246725 [patent_doc_number] => 06677678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Damascene structure using a sacrificial conductive layer' [patent_app_type] => B2 [patent_app_number] => 10/195763 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 5324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677678.pdf [firstpage_image] =>[orig_patent_app_number] => 10195763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1155420 [patent_doc_number] => 06764881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method for manufacturing electro ceramic components' [patent_app_type] => B2 [patent_app_number] => 10/193972 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1857 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764881.pdf [firstpage_image] =>[orig_patent_app_number] => 10193972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1367904 [patent_doc_number] => 06566266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method of polishing a layer comprising copper using an oxide inhibitor slurry' [patent_app_type] => B2 [patent_app_number] => 10/193368 [patent_app_country] => US [patent_app_date] => 2002-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2796 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566266.pdf [firstpage_image] =>[orig_patent_app_number] => 10193368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1110980 [patent_doc_number] => 06806163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Ion implant method for topographic feature corner rounding' [patent_app_type] => B2 [patent_app_number] => 10/190248 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3890 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806163.pdf [firstpage_image] =>[orig_patent_app_number] => 10190248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1095990 [patent_doc_number] => 06821856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of manufacturing semiconductor device having source/drain regions included in a semiconductor layer formed over an isolation insulating film and a semiconductor device fabricated thereby' [patent_app_type] => B2 [patent_app_number] => 10/188108 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 7764 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821856.pdf [firstpage_image] =>[orig_patent_app_number] => 10188108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6851566 [patent_doc_number] => 20030143769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Method for fabricating monolithic integrated semiconductor photonic device' [patent_app_type] => new [patent_app_number] => 10/188468 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4173 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20030143769.pdf [firstpage_image] =>[orig_patent_app_number] => 10188468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1130565 [patent_doc_number] => 06787464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method of forming silicide layers over a plurality of semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 10/189048 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5442 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787464.pdf [firstpage_image] =>[orig_patent_app_number] => 10189048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6753449 [patent_doc_number] => 20030001225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/180328 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 26185 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001225.pdf [firstpage_image] =>[orig_patent_app_number] => 10180328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824451 [patent_doc_number] => 20030235073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Memory structures' [patent_app_type] => new [patent_app_number] => 10/177239 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2940 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235073.pdf [firstpage_image] =>[orig_patent_app_number] => 10177239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7150197 [patent_doc_number] => 20040171255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Method for producing polymer-free area on a substrate' [patent_app_type] => new [patent_app_number] => 10/481848 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1873 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20040171255.pdf [firstpage_image] =>[orig_patent_app_number] => 10481848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634856 [patent_doc_number] => 06656762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method for manufacturing semiconductor image sensor with color filters and bonding pads' [patent_app_type] => B2 [patent_app_number] => 10/166618 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2438 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656762.pdf [firstpage_image] =>[orig_patent_app_number] => 10166618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1188813 [patent_doc_number] => 06734044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Multiple leadframe laminated IC package' [patent_app_type] => B1 [patent_app_number] => 10/166458 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 53 [patent_no_of_words] => 2494 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734044.pdf [firstpage_image] =>[orig_patent_app_number] => 10166458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6678576 [patent_doc_number] => 20030228717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Co-sputter deposition of metal-doped chalcogenides' [patent_app_type] => new [patent_app_number] => 10/164429 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4932 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20030228717.pdf [firstpage_image] =>[orig_patent_app_number] => 10164429 [rel_patent_id] =>[rel_patent_doc_number] =>)