Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1254258
[patent_doc_number] => 06670669
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-30
[patent_title] => 'Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate'
[patent_app_type] => B1
[patent_app_number] => 10/030117
[patent_app_country] => US
[patent_app_date] => 2002-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8992
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/670/06670669.pdf
[firstpage_image] =>[orig_patent_app_number] => 10030117
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/030117 | Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate | Jan 22, 2002 | Issued |
Array
(
[id] => 1108943
[patent_doc_number] => 06809376
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-26
[patent_title] => 'Semiconductor integrated circuit device and manufacture method therefore'
[patent_app_type] => B2
[patent_app_number] => 10/055717
[patent_app_country] => US
[patent_app_date] => 2002-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4956
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/809/06809376.pdf
[firstpage_image] =>[orig_patent_app_number] => 10055717
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055717 | Semiconductor integrated circuit device and manufacture method therefore | Jan 22, 2002 | Issued |
Array
(
[id] => 6785792
[patent_doc_number] => 20030137031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Semiconductor device having a die with a rhombic shape'
[patent_app_type] => new
[patent_app_number] => 10/052467
[patent_app_country] => US
[patent_app_date] => 2002-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2699
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20030137031.pdf
[firstpage_image] =>[orig_patent_app_number] => 10052467
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052467 | Semiconductor device having a die with a rhombic shape | Jan 22, 2002 | Abandoned |
Array
(
[id] => 1261494
[patent_doc_number] => 06664172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-16
[patent_title] => 'Method of forming a MOS transistor with improved threshold voltage stability'
[patent_app_type] => B2
[patent_app_number] => 09/683578
[patent_app_country] => US
[patent_app_date] => 2002-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3022
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/664/06664172.pdf
[firstpage_image] =>[orig_patent_app_number] => 09683578
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/683578 | Method of forming a MOS transistor with improved threshold voltage stability | Jan 21, 2002 | Issued |
Array
(
[id] => 1113781
[patent_doc_number] => 06803646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Semiconductor device having first chip secured within resin layer and second chip secured on resin layer'
[patent_app_type] => B2
[patent_app_number] => 10/052078
[patent_app_country] => US
[patent_app_date] => 2002-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3412
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/803/06803646.pdf
[firstpage_image] =>[orig_patent_app_number] => 10052078
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052078 | Semiconductor device having first chip secured within resin layer and second chip secured on resin layer | Jan 16, 2002 | Issued |
Array
(
[id] => 6659627
[patent_doc_number] => 20030134438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-17
[patent_title] => 'Rare earth metal oxide memory element based on charge storage and method for manufacturing same'
[patent_app_type] => new
[patent_app_number] => 10/042181
[patent_app_country] => US
[patent_app_date] => 2002-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2538
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20030134438.pdf
[firstpage_image] =>[orig_patent_app_number] => 10042181
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/042181 | Rare earth metal oxide memory element based on charge storage and method for manufacturing same | Jan 10, 2002 | Issued |
Array
(
[id] => 6348945
[patent_doc_number] => 20020056880
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-16
[patent_title] => 'Method for fabricating interconnect of capacitor'
[patent_app_type] => new
[patent_app_number] => 10/045899
[patent_app_country] => US
[patent_app_date] => 2002-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1476
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20020056880.pdf
[firstpage_image] =>[orig_patent_app_number] => 10045899
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/045899 | Method for fabricating interconnect of capacitor | Jan 10, 2002 | Abandoned |
Array
(
[id] => 1420538
[patent_doc_number] => 06521931
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-18
[patent_title] => 'Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme'
[patent_app_type] => B2
[patent_app_number] => 10/040447
[patent_app_country] => US
[patent_app_date] => 2002-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3580
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/521/06521931.pdf
[firstpage_image] =>[orig_patent_app_number] => 10040447
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/040447 | Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme | Jan 8, 2002 | Issued |
Array
(
[id] => 6306614
[patent_doc_number] => 20020094613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-18
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/034498
[patent_app_country] => US
[patent_app_date] => 2002-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 22819
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20020094613.pdf
[firstpage_image] =>[orig_patent_app_number] => 10034498
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/034498 | Method of making a thin film transistor using laser annealing | Jan 2, 2002 | Issued |
Array
(
[id] => 6080985
[patent_doc_number] => 20020081758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Method of manufacturing semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/025458
[patent_app_country] => US
[patent_app_date] => 2001-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 16822
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20020081758.pdf
[firstpage_image] =>[orig_patent_app_number] => 10025458
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/025458 | Method of manufacturing and testing semiconductor integrated circuit device | Dec 25, 2001 | Issued |
Array
(
[id] => 1209307
[patent_doc_number] => 06713357
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-30
[patent_title] => 'Method to reduce parasitic capacitance of MOS transistors'
[patent_app_type] => B1
[patent_app_number] => 10/023348
[patent_app_country] => US
[patent_app_date] => 2001-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 4465
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/713/06713357.pdf
[firstpage_image] =>[orig_patent_app_number] => 10023348
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/023348 | Method to reduce parasitic capacitance of MOS transistors | Dec 19, 2001 | Issued |
Array
(
[id] => 1089118
[patent_doc_number] => 06828199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-07
[patent_title] => 'Monos device having buried metal silicide bit line'
[patent_app_type] => B2
[patent_app_number] => 10/022798
[patent_app_country] => US
[patent_app_date] => 2001-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2290
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/828/06828199.pdf
[firstpage_image] =>[orig_patent_app_number] => 10022798
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/022798 | Monos device having buried metal silicide bit line | Dec 19, 2001 | Issued |
Array
(
[id] => 1277963
[patent_doc_number] => 06645854
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-11
[patent_title] => 'Formation of a vertical junction throuph process simulation based optimization of implant doses and energies'
[patent_app_type] => B1
[patent_app_number] => 10/025079
[patent_app_country] => US
[patent_app_date] => 2001-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2964
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/645/06645854.pdf
[firstpage_image] =>[orig_patent_app_number] => 10025079
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/025079 | Formation of a vertical junction throuph process simulation based optimization of implant doses and energies | Dec 18, 2001 | Issued |
Array
(
[id] => 1330259
[patent_doc_number] => 06600170
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-29
[patent_title] => 'CMOS with strained silicon channel NMOS and silicon germanium channel PMOS'
[patent_app_type] => B1
[patent_app_number] => 10/015808
[patent_app_country] => US
[patent_app_date] => 2001-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2888
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/600/06600170.pdf
[firstpage_image] =>[orig_patent_app_number] => 10015808
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/015808 | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS | Dec 16, 2001 | Issued |
Array
(
[id] => 1410411
[patent_doc_number] => 06534841
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Continuous antifuse material in memory structure'
[patent_app_type] => B1
[patent_app_number] => 10/017567
[patent_app_country] => US
[patent_app_date] => 2001-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 4164
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/534/06534841.pdf
[firstpage_image] =>[orig_patent_app_number] => 10017567
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/017567 | Continuous antifuse material in memory structure | Dec 13, 2001 | Issued |
Array
(
[id] => 1417025
[patent_doc_number] => 06509281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-21
[patent_title] => 'Techniques for improving adhesion of silicon dioxide to titanium'
[patent_app_type] => B2
[patent_app_number] => 10/016066
[patent_app_country] => US
[patent_app_date] => 2001-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 2353
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/509/06509281.pdf
[firstpage_image] =>[orig_patent_app_number] => 10016066
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/016066 | Techniques for improving adhesion of silicon dioxide to titanium | Dec 10, 2001 | Issued |
Array
(
[id] => 7632751
[patent_doc_number] => 06664583
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-16
[patent_title] => 'Metal oxynitride capacitor barrier layer'
[patent_app_type] => B2
[patent_app_number] => 09/997920
[patent_app_country] => US
[patent_app_date] => 2001-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 7783
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/664/06664583.pdf
[firstpage_image] =>[orig_patent_app_number] => 09997920
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/997920 | Metal oxynitride capacitor barrier layer | Nov 29, 2001 | Issued |
Array
(
[id] => 5918025
[patent_doc_number] => 20020113280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-22
[patent_title] => 'Metal oxynitride capacitor barrier layer'
[patent_app_type] => new
[patent_app_number] => 09/999281
[patent_app_country] => US
[patent_app_date] => 2001-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7862
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20020113280.pdf
[firstpage_image] =>[orig_patent_app_number] => 09999281
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/999281 | Metal oxynitride capacitor barrier layer | Nov 29, 2001 | Issued |
Array
(
[id] => 7627901
[patent_doc_number] => 06806536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-19
[patent_title] => 'Multiple-function electronic chip'
[patent_app_type] => B2
[patent_app_number] => 09/999208
[patent_app_country] => US
[patent_app_date] => 2001-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4564
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/806/06806536.pdf
[firstpage_image] =>[orig_patent_app_number] => 09999208
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/999208 | Multiple-function electronic chip | Nov 29, 2001 | Issued |
Array
(
[id] => 1315494
[patent_doc_number] => 06607965
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-19
[patent_title] => 'Methods of forming capacitors'
[patent_app_type] => B2
[patent_app_number] => 09/997965
[patent_app_country] => US
[patent_app_date] => 2001-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3283
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/607/06607965.pdf
[firstpage_image] =>[orig_patent_app_number] => 09997965
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/997965 | Methods of forming capacitors | Nov 28, 2001 | Issued |