Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5825893 [patent_doc_number] => 20020066920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Methods of forming dielectric materials, methods of forming capacitors, and capacitor constructions' [patent_app_type] => new [patent_app_number] => 09/997620 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3297 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066920.pdf [firstpage_image] =>[orig_patent_app_number] => 09997620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997620
Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer Nov 28, 2001 Issued
Array ( [id] => 1502225 [patent_doc_number] => 06486496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Polysilicon thin film transistor structure' [patent_app_type] => B2 [patent_app_number] => 09/994322 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3558 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486496.pdf [firstpage_image] =>[orig_patent_app_number] => 09994322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994322
Polysilicon thin film transistor structure Nov 25, 2001 Issued
Array ( [id] => 7400700 [patent_doc_number] => 20040023486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'METHOD OF IMPLANTATION AFTER COPPER SEED DEPOSITION' [patent_app_type] => new [patent_app_number] => 09/994358 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3701 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023486.pdf [firstpage_image] =>[orig_patent_app_number] => 09994358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994358
Method of implantation after copper seed deposition Nov 25, 2001 Issued
Array ( [id] => 1218023 [patent_doc_number] => 06707126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Semiconductor device including a PIN photodiode integrated with a MOS transistor' [patent_app_type] => B2 [patent_app_number] => 09/993928 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4661 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707126.pdf [firstpage_image] =>[orig_patent_app_number] => 09993928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/993928
Semiconductor device including a PIN photodiode integrated with a MOS transistor Nov 13, 2001 Issued
Array ( [id] => 1305931 [patent_doc_number] => 06621115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate' [patent_app_type] => B2 [patent_app_number] => 10/005495 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 8223 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621115.pdf [firstpage_image] =>[orig_patent_app_number] => 10005495 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005495
Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate Nov 5, 2001 Issued
Array ( [id] => 6790940 [patent_doc_number] => 20030086284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Three-dimensional, mask-programmed read only memory' [patent_app_type] => new [patent_app_number] => 10/010643 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3673 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20030086284.pdf [firstpage_image] =>[orig_patent_app_number] => 10010643 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010643
Three-dimensional, mask-programmed read only memory Nov 4, 2001 Issued
Array ( [id] => 975955 [patent_doc_number] => 06933572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Field-shielded SOI-MOS structure free from floating body effect, and method of fabrication therefor' [patent_app_type] => utility [patent_app_number] => 09/984778 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4033 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933572.pdf [firstpage_image] =>[orig_patent_app_number] => 09984778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984778
Field-shielded SOI-MOS structure free from floating body effect, and method of fabrication therefor Oct 30, 2001 Issued
Array ( [id] => 7612446 [patent_doc_number] => 06903390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Single metal programmability in a customizable integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/416144 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2431 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903390.pdf [firstpage_image] =>[orig_patent_app_number] => 10416144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/416144
Single metal programmability in a customizable integrated circuit device Oct 24, 2001 Issued
Array ( [id] => 5645856 [patent_doc_number] => 20060131588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Electrode and electron emission applications for n-type doped nanocrystalline materials' [patent_app_type] => utility [patent_app_number] => 10/398329 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131588.pdf [firstpage_image] =>[orig_patent_app_number] => 10398329 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/398329
Electrode and electron emission applications for n-type doped nanocrystalline materials Oct 8, 2001 Abandoned
Array ( [id] => 7631003 [patent_doc_number] => 06635929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Uniform thin film semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/955201 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 63 [patent_no_of_words] => 15699 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635929.pdf [firstpage_image] =>[orig_patent_app_number] => 09955201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955201
Uniform thin film semiconductor device Sep 18, 2001 Issued
Array ( [id] => 645289 [patent_doc_number] => 07119008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Integrating metal layers with ultra low-K dielectrics' [patent_app_type] => utility [patent_app_number] => 10/380848 [patent_app_country] => US [patent_app_date] => 2001-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 76 [patent_no_of_words] => 8322 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119008.pdf [firstpage_image] =>[orig_patent_app_number] => 10380848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/380848
Integrating metal layers with ultra low-K dielectrics Sep 17, 2001 Issued
Array ( [id] => 6778802 [patent_doc_number] => 20030049883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Semiconductor package production method and semiconductor package' [patent_app_type] => new [patent_app_number] => 09/952038 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4475 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20030049883.pdf [firstpage_image] =>[orig_patent_app_number] => 09952038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952038
Method of forming a semiconductor package Sep 10, 2001 Issued
Array ( [id] => 6745240 [patent_doc_number] => 20030022423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Electro ceramic components' [patent_app_type] => new [patent_app_number] => 09/919038 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1866 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022423.pdf [firstpage_image] =>[orig_patent_app_number] => 09919038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919038
Electro ceramic components Jul 29, 2001 Issued
Array ( [id] => 1343937 [patent_doc_number] => 06590251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Semiconductor devices having metal layers as barrier layers on upper or lower electrodes of capacitors' [patent_app_type] => B2 [patent_app_number] => 09/911313 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 9200 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590251.pdf [firstpage_image] =>[orig_patent_app_number] => 09911313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911313
Semiconductor devices having metal layers as barrier layers on upper or lower electrodes of capacitors Jul 22, 2001 Issued
Array ( [id] => 1594327 [patent_doc_number] => 06383860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/908607 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 96 [patent_figures_cnt] => 133 [patent_no_of_words] => 21955 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383860.pdf [firstpage_image] =>[orig_patent_app_number] => 09908607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908607
Semiconductor device and method of manufacturing the same Jul 19, 2001 Issued
Array ( [id] => 6137740 [patent_doc_number] => 20020000583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'System with meshed power and signal buses on cell array' [patent_app_type] => new [patent_app_number] => 09/909191 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9280 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000583.pdf [firstpage_image] =>[orig_patent_app_number] => 09909191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909191
System with meshed power and signal buses on cell array Jul 18, 2001 Issued
Array ( [id] => 6123216 [patent_doc_number] => 20020074547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device' [patent_app_type] => new [patent_app_number] => 09/901126 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 20978 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074547.pdf [firstpage_image] =>[orig_patent_app_number] => 09901126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901126
Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device Jul 9, 2001 Abandoned
Array ( [id] => 1419017 [patent_doc_number] => 06525368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'High density flash EEPROM array with source side injection' [patent_app_type] => B1 [patent_app_number] => 09/892685 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3970 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525368.pdf [firstpage_image] =>[orig_patent_app_number] => 09892685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892685
High density flash EEPROM array with source side injection Jun 26, 2001 Issued
Array ( [id] => 7065013 [patent_doc_number] => 20010044221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks' [patent_app_type] => new [patent_app_number] => 09/891570 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2388 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044221.pdf [firstpage_image] =>[orig_patent_app_number] => 09891570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891570
Semiconductor processing methods of forming an utilizing antireflective material layers, and methods of forming transistor gate stacks Jun 24, 2001 Issued
Array ( [id] => 1529509 [patent_doc_number] => 06479881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry' [patent_app_type] => B2 [patent_app_number] => 09/882678 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4664 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479881.pdf [firstpage_image] =>[orig_patent_app_number] => 09882678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882678
Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry Jun 17, 2001 Issued
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