Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1374853
[patent_doc_number] => 06566735
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-20
[patent_title] => 'Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film'
[patent_app_type] => B1
[patent_app_number] => 09/715372
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 5068
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/566/06566735.pdf
[firstpage_image] =>[orig_patent_app_number] => 09715372
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715372 | Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film | Nov 16, 2000 | Issued |
Array
(
[id] => 1480645
[patent_doc_number] => 06452263
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Radiation shield and radiation shielded integrated circuit device'
[patent_app_type] => B1
[patent_app_number] => 09/715401
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2424
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/452/06452263.pdf
[firstpage_image] =>[orig_patent_app_number] => 09715401
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715401 | Radiation shield and radiation shielded integrated circuit device | Nov 16, 2000 | Issued |
Array
(
[id] => 1576362
[patent_doc_number] => 06469366
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-22
[patent_title] => 'Bipolar transistor with collector diffusion layer formed deep in the substrate'
[patent_app_type] => B1
[patent_app_number] => 09/714112
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 17987
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/469/06469366.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714112 | Bipolar transistor with collector diffusion layer formed deep in the substrate | Nov 16, 2000 | Issued |
Array
(
[id] => 1502367
[patent_doc_number] => 06486543
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Packaged semiconductor device having bent leads'
[patent_app_type] => B1
[patent_app_number] => 09/700631
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 30
[patent_no_of_words] => 9207
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/486/06486543.pdf
[firstpage_image] =>[orig_patent_app_number] => 09700631
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/700631 | Packaged semiconductor device having bent leads | Nov 16, 2000 | Issued |
Array
(
[id] => 1281351
[patent_doc_number] => 06646326
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-11
[patent_title] => 'Method and system for providing source/drain-gate spatial overlap engineering for low-power devices'
[patent_app_type] => B1
[patent_app_number] => 09/714361
[patent_app_country] => US
[patent_app_date] => 2000-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 24
[patent_no_of_words] => 7955
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/646/06646326.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714361
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714361 | Method and system for providing source/drain-gate spatial overlap engineering for low-power devices | Nov 14, 2000 | Issued |
Array
(
[id] => 1462487
[patent_doc_number] => 06350650
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Method for fabricating a semiconductor memory device'
[patent_app_type] => B1
[patent_app_number] => 09/710958
[patent_app_country] => US
[patent_app_date] => 2000-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 25
[patent_no_of_words] => 5489
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350650.pdf
[firstpage_image] =>[orig_patent_app_number] => 09710958
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/710958 | Method for fabricating a semiconductor memory device | Nov 13, 2000 | Issued |
Array
(
[id] => 1419280
[patent_doc_number] => 06525388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'Compound semiconductor device having diode connected between emitter and collector of bipolar transistor'
[patent_app_type] => B1
[patent_app_number] => 09/708420
[patent_app_country] => US
[patent_app_date] => 2000-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3542
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09708420
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/708420 | Compound semiconductor device having diode connected between emitter and collector of bipolar transistor | Nov 8, 2000 | Issued |
Array
(
[id] => 1403613
[patent_doc_number] => 06531715
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Multilayer contact electrode for compound semiconductors and production method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/707811
[patent_app_country] => US
[patent_app_date] => 2000-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3154
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531715.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707811
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707811 | Multilayer contact electrode for compound semiconductors and production method thereof | Nov 6, 2000 | Issued |
Array
(
[id] => 1419042
[patent_doc_number] => 06525370
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'Semiconductor device including transistor with composite gate structure and transistor with single gate structure and method for manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/706810
[patent_app_country] => US
[patent_app_date] => 2000-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 4774
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525370.pdf
[firstpage_image] =>[orig_patent_app_number] => 09706810
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706810 | Semiconductor device including transistor with composite gate structure and transistor with single gate structure and method for manufacturing the same | Nov 6, 2000 | Issued |
Array
(
[id] => 1468565
[patent_doc_number] => 06459136
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Single metal programmability in a customizable integrated circuit device'
[patent_app_type] => B1
[patent_app_number] => 09/707762
[patent_app_country] => US
[patent_app_date] => 2000-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2395
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459136.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707762
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707762 | Single metal programmability in a customizable integrated circuit device | Nov 6, 2000 | Issued |
Array
(
[id] => 1528102
[patent_doc_number] => 06479369
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Shallow trench isolation (STI) and method of forming the same'
[patent_app_type] => B1
[patent_app_number] => 09/705782
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 30
[patent_no_of_words] => 5731
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/479/06479369.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705782
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705782 | Shallow trench isolation (STI) and method of forming the same | Nov 5, 2000 | Issued |
Array
(
[id] => 1389260
[patent_doc_number] => 06544812
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Single unit automated assembly of flex enhanced ball grid array packages'
[patent_app_type] => B1
[patent_app_number] => 09/706220
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 4900
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/544/06544812.pdf
[firstpage_image] =>[orig_patent_app_number] => 09706220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706220 | Single unit automated assembly of flex enhanced ball grid array packages | Nov 5, 2000 | Issued |
Array
(
[id] => 1480619
[patent_doc_number] => 06452258
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Ultra-thin composite surface finish for electronic packaging'
[patent_app_type] => B1
[patent_app_number] => 09/707042
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2832
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/452/06452258.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707042
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707042 | Ultra-thin composite surface finish for electronic packaging | Nov 5, 2000 | Issued |
Array
(
[id] => 1390674
[patent_doc_number] => 06544885
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Polished hard mask process for conductor layer patterning'
[patent_app_type] => B1
[patent_app_number] => 09/706498
[patent_app_country] => US
[patent_app_date] => 2000-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3691
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/544/06544885.pdf
[firstpage_image] =>[orig_patent_app_number] => 09706498
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706498 | Polished hard mask process for conductor layer patterning | Nov 2, 2000 | Issued |
Array
(
[id] => 1590884
[patent_doc_number] => 06483177
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Leaded semiconductor packages and method of trimming and singulating such packages'
[patent_app_type] => B1
[patent_app_number] => 09/705251
[patent_app_country] => US
[patent_app_date] => 2000-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 3719
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/483/06483177.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705251
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705251 | Leaded semiconductor packages and method of trimming and singulating such packages | Nov 1, 2000 | Issued |
Array
(
[id] => 1381504
[patent_doc_number] => 06551868
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Vertical power component manufacturing method'
[patent_app_type] => B1
[patent_app_number] => 09/705292
[patent_app_country] => US
[patent_app_date] => 2000-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1849
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/551/06551868.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705292
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705292 | Vertical power component manufacturing method | Nov 1, 2000 | Issued |
Array
(
[id] => 7643572
[patent_doc_number] => 06429469
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Optical Proximity Correction Structures Having Decoupling Capacitors'
[patent_app_type] => B1
[patent_app_number] => 09/705031
[patent_app_country] => US
[patent_app_date] => 2000-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2824
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429469.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705031
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705031 | Optical Proximity Correction Structures Having Decoupling Capacitors | Nov 1, 2000 | Issued |
Array
(
[id] => 1491877
[patent_doc_number] => 06417566
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Void eliminating seed layer and conductor core integrated circuit interconnects'
[patent_app_type] => B1
[patent_app_number] => 09/705121
[patent_app_country] => US
[patent_app_date] => 2000-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3064
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/417/06417566.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705121 | Void eliminating seed layer and conductor core integrated circuit interconnects | Oct 31, 2000 | Issued |
Array
(
[id] => 4328675
[patent_doc_number] => 06312974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated'
[patent_app_type] => 1
[patent_app_number] => 9/699128
[patent_app_country] => US
[patent_app_date] => 2000-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5008
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/312/06312974.pdf
[firstpage_image] =>[orig_patent_app_number] => 699128
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/699128 | Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated | Oct 25, 2000 | Issued |
Array
(
[id] => 1424308
[patent_doc_number] => 06503808
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Lateral bipolar transistor and method for producing the same'
[patent_app_type] => B1
[patent_app_number] => 09/687251
[patent_app_country] => US
[patent_app_date] => 2000-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 43
[patent_no_of_words] => 12063
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/503/06503808.pdf
[firstpage_image] =>[orig_patent_app_number] => 09687251
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/687251 | Lateral bipolar transistor and method for producing the same | Oct 12, 2000 | Issued |