Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1459579 [patent_doc_number] => 06391782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Process for forming multiple active lines and gate-all-around MOSFET' [patent_app_type] => B1 [patent_app_number] => 09/597598 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391782.pdf [firstpage_image] =>[orig_patent_app_number] => 09597598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597598
Process for forming multiple active lines and gate-all-around MOSFET Jun 19, 2000 Issued
Array ( [id] => 1441011 [patent_doc_number] => 06335247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Integrated circuit vertical trench device and method of forming thereof' [patent_app_type] => B1 [patent_app_number] => 09/597389 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3967 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335247.pdf [firstpage_image] =>[orig_patent_app_number] => 09597389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597389
Integrated circuit vertical trench device and method of forming thereof Jun 18, 2000 Issued
Array ( [id] => 1462621 [patent_doc_number] => 06350684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Graded/stepped silicide process to improve MOS transistor' [patent_app_type] => B1 [patent_app_number] => 09/594868 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1790 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350684.pdf [firstpage_image] =>[orig_patent_app_number] => 09594868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/594868
Graded/stepped silicide process to improve MOS transistor Jun 14, 2000 Issued
Array ( [id] => 4381679 [patent_doc_number] => 06294461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Structure for contact formation using a silicon-germanium alloy' [patent_app_type] => 1 [patent_app_number] => 9/592748 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5697 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294461.pdf [firstpage_image] =>[orig_patent_app_number] => 592748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592748
Structure for contact formation using a silicon-germanium alloy Jun 12, 2000 Issued
Array ( [id] => 1603253 [patent_doc_number] => 06433433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Semiconductor device with misaligned via hole' [patent_app_type] => B1 [patent_app_number] => 09/593322 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5806 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433433.pdf [firstpage_image] =>[orig_patent_app_number] => 09593322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593322
Semiconductor device with misaligned via hole Jun 12, 2000 Issued
Array ( [id] => 1441113 [patent_doc_number] => 06335297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method for forming conductive line of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/592438 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 2861 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335297.pdf [firstpage_image] =>[orig_patent_app_number] => 09592438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592438
Method for forming conductive line of semiconductor device Jun 11, 2000 Issued
Array ( [id] => 4407769 [patent_doc_number] => 06309896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method of manufacturing a ferroelectric film' [patent_app_type] => 1 [patent_app_number] => 9/585548 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 1628 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309896.pdf [firstpage_image] =>[orig_patent_app_number] => 585548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585548
Method of manufacturing a ferroelectric film Jun 1, 2000 Issued
Array ( [id] => 4326187 [patent_doc_number] => 06319744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method for manufacturing a thermoelectric semiconductor material or element and method for manufacturing a thermoelectric module' [patent_app_type] => 1 [patent_app_number] => 9/584398 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5442 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319744.pdf [firstpage_image] =>[orig_patent_app_number] => 584398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584398
Method for manufacturing a thermoelectric semiconductor material or element and method for manufacturing a thermoelectric module May 31, 2000 Issued
Array ( [id] => 4324432 [patent_doc_number] => 06329226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method for fabricating a thin-film transistor' [patent_app_type] => 1 [patent_app_number] => 9/585159 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5696 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329226.pdf [firstpage_image] =>[orig_patent_app_number] => 585159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585159
Method for fabricating a thin-film transistor May 31, 2000 Issued
Array ( [id] => 4324900 [patent_doc_number] => 06329259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Collector-up RF power transistor' [patent_app_type] => 1 [patent_app_number] => 9/583648 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3247 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329259.pdf [firstpage_image] =>[orig_patent_app_number] => 583648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583648
Collector-up RF power transistor May 29, 2000 Issued
Array ( [id] => 4382030 [patent_doc_number] => 06294483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method for preventing delamination of APCVD BPSG films' [patent_app_type] => 1 [patent_app_number] => 9/567418 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3219 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294483.pdf [firstpage_image] =>[orig_patent_app_number] => 567418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567418
Method for preventing delamination of APCVD BPSG films May 8, 2000 Issued
Array ( [id] => 1549746 [patent_doc_number] => 06346463 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method for forming a semiconductor device with a tailored well profile' [patent_app_type] => B1 [patent_app_number] => 09/565858 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3063 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346463.pdf [firstpage_image] =>[orig_patent_app_number] => 09565858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565858
Method for forming a semiconductor device with a tailored well profile May 4, 2000 Issued
Array ( [id] => 4267798 [patent_doc_number] => 06306779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for nano-structuring amorphous carbon layers' [patent_app_type] => 1 [patent_app_number] => 9/463868 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1985 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306779.pdf [firstpage_image] =>[orig_patent_app_number] => 463868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/463868
Method for nano-structuring amorphous carbon layers May 2, 2000 Issued
Array ( [id] => 4269641 [patent_doc_number] => 06245613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Field effect transistor having a floating gate' [patent_app_type] => 1 [patent_app_number] => 9/556698 [patent_app_country] => US [patent_app_date] => 2000-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2505 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245613.pdf [firstpage_image] =>[orig_patent_app_number] => 556698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556698
Field effect transistor having a floating gate Apr 23, 2000 Issued
Array ( [id] => 1441046 [patent_doc_number] => 06335263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials' [patent_app_type] => B1 [patent_app_number] => 09/535658 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3661 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335263.pdf [firstpage_image] =>[orig_patent_app_number] => 09535658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535658
Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials Mar 21, 2000 Issued
Array ( [id] => 4310249 [patent_doc_number] => 06316317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Nonvolatile semiconductor memory device including two-transistor type memory cells and its manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/526419 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 53 [patent_no_of_words] => 6486 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316317.pdf [firstpage_image] =>[orig_patent_app_number] => 526419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526419
Nonvolatile semiconductor memory device including two-transistor type memory cells and its manufacturing method Mar 14, 2000 Issued
Array ( [id] => 4369384 [patent_doc_number] => 06287965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor' [patent_app_type] => 1 [patent_app_number] => 9/511598 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 9246 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287965.pdf [firstpage_image] =>[orig_patent_app_number] => 511598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511598
Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor Feb 22, 2000 Issued
Array ( [id] => 1491797 [patent_doc_number] => 06417537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Metal oxynitride capacitor barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/484815 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7750 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 27 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417537.pdf [firstpage_image] =>[orig_patent_app_number] => 09484815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484815
Metal oxynitride capacitor barrier layer Jan 17, 2000 Issued
Array ( [id] => 4366896 [patent_doc_number] => 06274495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for fabricating a device on a substrate' [patent_app_type] => 1 [patent_app_number] => 9/484778 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 9419 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274495.pdf [firstpage_image] =>[orig_patent_app_number] => 484778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484778
Method for fabricating a device on a substrate Jan 17, 2000 Issued
Array ( [id] => 1550420 [patent_doc_number] => 06399473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method of producing a II-VI semiconductor component containing selenium and/or sulrfur' [patent_app_type] => B1 [patent_app_number] => 09/480758 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4010 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399473.pdf [firstpage_image] =>[orig_patent_app_number] => 09480758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480758
Method of producing a II-VI semiconductor component containing selenium and/or sulrfur Jan 9, 2000 Issued
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