Christopher E Dunay
Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875 |
Total Applications | 722 |
Issued Applications | 487 |
Pending Applications | 67 |
Abandoned Applications | 168 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1459579
[patent_doc_number] => 06391782
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Process for forming multiple active lines and gate-all-around MOSFET'
[patent_app_type] => B1
[patent_app_number] => 09/597598
[patent_app_country] => US
[patent_app_date] => 2000-06-20
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[pdf_file] => patents/06/391/06391782.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/597598 | Process for forming multiple active lines and gate-all-around MOSFET | Jun 19, 2000 | Issued |
Array
(
[id] => 1441011
[patent_doc_number] => 06335247
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[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Integrated circuit vertical trench device and method of forming thereof'
[patent_app_type] => B1
[patent_app_number] => 09/597389
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[patent_app_date] => 2000-06-19
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[pdf_file] => patents/06/335/06335247.pdf
[firstpage_image] =>[orig_patent_app_number] => 09597389
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/597389 | Integrated circuit vertical trench device and method of forming thereof | Jun 18, 2000 | Issued |
Array
(
[id] => 1462621
[patent_doc_number] => 06350684
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Graded/stepped silicide process to improve MOS transistor'
[patent_app_type] => B1
[patent_app_number] => 09/594868
[patent_app_country] => US
[patent_app_date] => 2000-06-15
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[pdf_file] => patents/06/350/06350684.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/594868 | Graded/stepped silicide process to improve MOS transistor | Jun 14, 2000 | Issued |
Array
(
[id] => 4381679
[patent_doc_number] => 06294461
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Structure for contact formation using a silicon-germanium alloy'
[patent_app_type] => 1
[patent_app_number] => 9/592748
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[patent_app_date] => 2000-06-13
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 1603253
[patent_doc_number] => 06433433
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Semiconductor device with misaligned via hole'
[patent_app_type] => B1
[patent_app_number] => 09/593322
[patent_app_country] => US
[patent_app_date] => 2000-06-13
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[firstpage_image] =>[orig_patent_app_number] => 09593322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/593322 | Semiconductor device with misaligned via hole | Jun 12, 2000 | Issued |
Array
(
[id] => 1441113
[patent_doc_number] => 06335297
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Method for forming conductive line of semiconductor device'
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[patent_app_number] => 09/592438
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/592438 | Method for forming conductive line of semiconductor device | Jun 11, 2000 | Issued |
Array
(
[id] => 4407769
[patent_doc_number] => 06309896
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[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Method of manufacturing a ferroelectric film'
[patent_app_type] => 1
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[pdf_file] => patents/06/309/06309896.pdf
[firstpage_image] =>[orig_patent_app_number] => 585548
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/585548 | Method of manufacturing a ferroelectric film | Jun 1, 2000 | Issued |
Array
(
[id] => 4326187
[patent_doc_number] => 06319744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Method for manufacturing a thermoelectric semiconductor material or element and method for manufacturing a thermoelectric module'
[patent_app_type] => 1
[patent_app_number] => 9/584398
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[pdf_file] => patents/06/319/06319744.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/584398 | Method for manufacturing a thermoelectric semiconductor material or element and method for manufacturing a thermoelectric module | May 31, 2000 | Issued |
Array
(
[id] => 4324432
[patent_doc_number] => 06329226
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Method for fabricating a thin-film transistor'
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[patent_app_number] => 9/585159
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/585159 | Method for fabricating a thin-film transistor | May 31, 2000 | Issued |
Array
(
[id] => 4324900
[patent_doc_number] => 06329259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Collector-up RF power transistor'
[patent_app_type] => 1
[patent_app_number] => 9/583648
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583648 | Collector-up RF power transistor | May 29, 2000 | Issued |
Array
(
[id] => 4382030
[patent_doc_number] => 06294483
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Method for preventing delamination of APCVD BPSG films'
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[patent_app_number] => 9/567418
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[pdf_file] => patents/06/294/06294483.pdf
[firstpage_image] =>[orig_patent_app_number] => 567418
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/567418 | Method for preventing delamination of APCVD BPSG films | May 8, 2000 | Issued |
Array
(
[id] => 1549746
[patent_doc_number] => 06346463
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[patent_issue_date] => 2002-02-12
[patent_title] => 'Method for forming a semiconductor device with a tailored well profile'
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Array
(
[id] => 4267798
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[patent_issue_date] => 2001-10-23
[patent_title] => 'Method for nano-structuring amorphous carbon layers'
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Array
(
[id] => 4269641
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[patent_title] => 'Field effect transistor having a floating gate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/556698 | Field effect transistor having a floating gate | Apr 23, 2000 | Issued |
Array
(
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Array
(
[id] => 4310249
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[patent_issue_date] => 2001-11-13
[patent_title] => 'Nonvolatile semiconductor memory device including two-transistor type memory cells and its manufacturing method'
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Array
(
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[patent_title] => 'Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor'
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Array
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