Christopher E Dunay

Array ( [id] => 4291788 [patent_doc_number] => 06180446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing' [patent_app_type] => 1 [patent_app_number] => 9/211911 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 3740 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180446.pdf [firstpage_image] =>[orig_patent_app_number] => 211911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405660 [patent_doc_number] => 06171898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing' [patent_app_type] => 1 [patent_app_number] => 9/212031 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171898.pdf [firstpage_image] =>[orig_patent_app_number] => 212031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408514 [patent_doc_number] => 06228699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Cross leakage of capacitors in DRAM or embedded DRAM' [patent_app_type] => 1 [patent_app_number] => 9/210703 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1551 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228699.pdf [firstpage_image] =>[orig_patent_app_number] => 210703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4182605 [patent_doc_number] => 06150249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Methods of forming niobium-near noble metal contact structures for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/183081 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3917 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150249.pdf [firstpage_image] =>[orig_patent_app_number] => 183081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4358894 [patent_doc_number] => 06255215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor device having silicide layers formed using a collimated metal layer' [patent_app_type] => 1 [patent_app_number] => 9/175652 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2435 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255215.pdf [firstpage_image] =>[orig_patent_app_number] => 175652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1594424 [patent_doc_number] => 06383883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of reducing junction capacitance of source/drain region' [patent_app_type] => B1 [patent_app_number] => 09/173831 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383883.pdf [firstpage_image] =>[orig_patent_app_number] => 09173831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380545 [patent_doc_number] => 06261865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Multi chip semiconductor package and method of construction' [patent_app_type] => 1 [patent_app_number] => 9/167258 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3894 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261865.pdf [firstpage_image] =>[orig_patent_app_number] => 167258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4312978 [patent_doc_number] => 06242347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method for cleaning a process chamber' [patent_app_type] => 1 [patent_app_number] => 9/163711 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4523 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242347.pdf [firstpage_image] =>[orig_patent_app_number] => 163711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237003 [patent_doc_number] => 06090666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for fabricating semiconductor nanocrystal and semiconductor memory device using the semiconductor nanocrystal' [patent_app_type] => 1 [patent_app_number] => 9/163552 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 8569 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090666.pdf [firstpage_image] =>[orig_patent_app_number] => 163552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4169161 [patent_doc_number] => 06140191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions' [patent_app_type] => 1 [patent_app_number] => 9/157973 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6289 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140191.pdf [firstpage_image] =>[orig_patent_app_number] => 157973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293069 [patent_doc_number] => 06197602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Burn-in method for microwave semiconductor transistor' [patent_app_type] => 1 [patent_app_number] => 9/148793 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5580 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197602.pdf [firstpage_image] =>[orig_patent_app_number] => 148793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4287133 [patent_doc_number] => 06268282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks' [patent_app_type] => 1 [patent_app_number] => 9/146841 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268282.pdf [firstpage_image] =>[orig_patent_app_number] => 146841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4275714 [patent_doc_number] => 06281100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Semiconductor processing methods' [patent_app_type] => 1 [patent_app_number] => 9/146842 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2699 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281100.pdf [firstpage_image] =>[orig_patent_app_number] => 146842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407822 [patent_doc_number] => 06265232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Yield based, in-line defect sampling method' [patent_app_type] => 1 [patent_app_number] => 9/138295 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3324 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265232.pdf [firstpage_image] =>[orig_patent_app_number] => 138295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359174 [patent_doc_number] => 06169020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Methods of fabricating integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region' [patent_app_type] => 1 [patent_app_number] => 9/137598 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4964 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169020.pdf [firstpage_image] =>[orig_patent_app_number] => 137598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4358552 [patent_doc_number] => 06168977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method of manufacturing a semiconductor device having conductive patterns' [patent_app_type] => 1 [patent_app_number] => 9/135553 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/168/06168977.pdf [firstpage_image] =>[orig_patent_app_number] => 135553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294042 [patent_doc_number] => 06197671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Multiple finger polysilicon gate structure and method of making' [patent_app_type] => 1 [patent_app_number] => 9/132732 [patent_app_country] => US [patent_app_date] => 1998-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197671.pdf [firstpage_image] =>[orig_patent_app_number] => 132732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4106703 [patent_doc_number] => 06022785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method of fabricating a metal-oxide-semiconductor transistor' [patent_app_type] => 1 [patent_app_number] => 9/126462 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2536 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022785.pdf [firstpage_image] =>[orig_patent_app_number] => 126462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301324 [patent_doc_number] => 06251693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Semiconductor processing methods and semiconductor defect detection methods' [patent_app_type] => 1 [patent_app_number] => 9/126983 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1755 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251693.pdf [firstpage_image] =>[orig_patent_app_number] => 126983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4130702 [patent_doc_number] => 06121063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method of testing a ball grid array IC' [patent_app_type] => 1 [patent_app_number] => 9/124876 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 2235 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121063.pdf [firstpage_image] =>[orig_patent_app_number] => 124876 [rel_patent_id] =>[rel_patent_doc_number] =>)