Search

Christopher E. Lee

Examiner (ID: 4808)

Most Active Art Unit
3992
Art Unit(s)
2111, 2181, 2189, 2112, 3992
Total Applications
369
Issued Applications
281
Pending Applications
10
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 836199 [patent_doc_number] => 07398343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Interrupt processing system' [patent_app_type] => utility [patent_app_number] => 11/324667 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7026 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/398/07398343.pdf [firstpage_image] =>[orig_patent_app_number] => 11324667 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324667
Interrupt processing system Jan 2, 2006 Issued
Array ( [id] => 918646 [patent_doc_number] => 07328296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-05 [patent_title] => 'Interrupt processing system' [patent_app_type] => utility [patent_app_number] => 11/324695 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7025 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/328/07328296.pdf [firstpage_image] =>[orig_patent_app_number] => 11324695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324695
Interrupt processing system Jan 2, 2006 Issued
Array ( [id] => 447251 [patent_doc_number] => 07257662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Status reporting apparatus and status reporting method' [patent_app_type] => utility [patent_app_number] => 11/322360 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3490 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257662.pdf [firstpage_image] =>[orig_patent_app_number] => 11322360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322360
Status reporting apparatus and status reporting method Jan 2, 2006 Issued
Array ( [id] => 921863 [patent_doc_number] => 07325084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-29 [patent_title] => 'Messages signaling interrupt (MSI) processing system' [patent_app_type] => utility [patent_app_number] => 11/324666 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7024 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325084.pdf [firstpage_image] =>[orig_patent_app_number] => 11324666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324666
Messages signaling interrupt (MSI) processing system Jan 2, 2006 Issued
90/007849 AUTOMATIC DATA TRANSMISSION IN RESPONSE TO CONTENT OF ELECTRONIC FORMS SATISFYING CRITERIA Dec 13, 2005 Issued
90/007841 METHOD AND APPARATUS FOR ATTENTUATING EXTERNAL ORIGIN NOISE REACHING THE EARDRUM, AND FOR IMPROVING INTELLIGIBILITY OF ELECTRO-ACOUSTIC COMMUNICATIONS Dec 11, 2005 Issued
Array ( [id] => 478210 [patent_doc_number] => 07231482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Method and system for monitoring and transmitting utility status via universal communications interface' [patent_app_type] => utility [patent_app_number] => 11/245796 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2652 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231482.pdf [firstpage_image] =>[orig_patent_app_number] => 11245796 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245796
Method and system for monitoring and transmitting utility status via universal communications interface Oct 6, 2005 Issued
Array ( [id] => 392770 [patent_doc_number] => 07302510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Fair hierarchical arbiter' [patent_app_type] => utility [patent_app_number] => 11/239615 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302510.pdf [firstpage_image] =>[orig_patent_app_number] => 11239615 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239615
Fair hierarchical arbiter Sep 28, 2005 Issued
95/000112 COAXIAL CONNECTOR HAVING DETACHABLE LOCKING SLEEVE Sep 19, 2005 Issued
Array ( [id] => 5127641 [patent_doc_number] => 20070239912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Reconfigurable virtual backplane architecture' [patent_app_type] => utility [patent_app_number] => 11/211850 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20070239912.pdf [firstpage_image] =>[orig_patent_app_number] => 11211850 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211850
Reconfigurable virtual backplane architecture Aug 23, 2005 Issued
Array ( [id] => 619671 [patent_doc_number] => 07146451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'PCI bridge and data transfer methods' [patent_app_type] => utility [patent_app_number] => 11/181843 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3198 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146451.pdf [firstpage_image] =>[orig_patent_app_number] => 11181843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181843
PCI bridge and data transfer methods Jul 14, 2005 Issued
Array ( [id] => 5143616 [patent_doc_number] => 20070005832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Frame order processing apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 11/171959 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3813 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20070005832.pdf [firstpage_image] =>[orig_patent_app_number] => 11171959 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171959
Frame order processing apparatus, systems, and methods Jun 28, 2005 Issued
Array ( [id] => 4996037 [patent_doc_number] => 20070011382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Hierarchical memory access via pipelining with deferred arbitration' [patent_app_type] => utility [patent_app_number] => 11/165859 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6714 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011382.pdf [firstpage_image] =>[orig_patent_app_number] => 11165859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165859
Hierarchical memory access via pipelining with deferred arbitration Jun 23, 2005 Issued
Array ( [id] => 5846840 [patent_doc_number] => 20060123175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Universal serial bus access device with selectable modes' [patent_app_type] => utility [patent_app_number] => 11/152232 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 877 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123175.pdf [firstpage_image] =>[orig_patent_app_number] => 11152232 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152232
Universal serial bus access device with selectable modes Jun 14, 2005 Abandoned
Array ( [id] => 431305 [patent_doc_number] => 07269679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'PCI-X error correcting code (ECC) pin sharing configuration' [patent_app_type] => utility [patent_app_number] => 11/151317 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3259 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269679.pdf [firstpage_image] =>[orig_patent_app_number] => 11151317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151317
PCI-X error correcting code (ECC) pin sharing configuration Jun 13, 2005 Issued
Array ( [id] => 472812 [patent_doc_number] => 07234015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'PCIXCAP pin input sharing configuration for additional use as PCI hot plug interface pin input' [patent_app_type] => utility [patent_app_number] => 11/151316 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3668 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/234/07234015.pdf [firstpage_image] =>[orig_patent_app_number] => 11151316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151316
PCIXCAP pin input sharing configuration for additional use as PCI hot plug interface pin input Jun 13, 2005 Issued
Array ( [id] => 912117 [patent_doc_number] => 07334073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Method of and apparatus for interfacing buses operating at different speeds' [patent_app_type] => utility [patent_app_number] => 11/142463 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5467 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/334/07334073.pdf [firstpage_image] =>[orig_patent_app_number] => 11142463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/142463
Method of and apparatus for interfacing buses operating at different speeds Jun 1, 2005 Issued
90/007561 DETECTING CONTRABAND BY EMPLOYING INTERACTIVE MULTIPROBE TOMOGRAPHY May 26, 2005 Issued
Array ( [id] => 5610202 [patent_doc_number] => 20060271718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Method of preventing error propagation in a PCI / PCI-X / PCI express link' [patent_app_type] => utility [patent_app_number] => 11/139222 [patent_app_country] => US [patent_app_date] => 2005-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2666 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271718.pdf [firstpage_image] =>[orig_patent_app_number] => 11139222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/139222
Method of preventing error propagation in a PCI / PCI-X / PCI express link May 26, 2005 Abandoned
Array ( [id] => 5734554 [patent_doc_number] => 20060259671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Packet switch with multiple addressable components' [patent_app_type] => utility [patent_app_number] => 11/129600 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13407 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259671.pdf [firstpage_image] =>[orig_patent_app_number] => 11129600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129600
Packet switch with multiple addressable components May 12, 2005 Issued
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