
Christopher E. Lee
Examiner (ID: 4808)
| Most Active Art Unit | 3992 |
| Art Unit(s) | 2111, 2181, 2189, 2112, 3992 |
| Total Applications | 369 |
| Issued Applications | 281 |
| Pending Applications | 10 |
| Abandoned Applications | 77 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 451036
[patent_doc_number] => 07254663
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes'
[patent_app_type] => utility
[patent_app_number] => 10/897341
[patent_app_country] => US
[patent_app_date] => 2004-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6313
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[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/254/07254663.pdf
[firstpage_image] =>[orig_patent_app_number] => 10897341
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/897341 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Jul 21, 2004 | Issued |
Array
(
[id] => 5739886
[patent_doc_number] => 20060010277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Isolation of input/output adapter interrupt domains'
[patent_app_type] => utility
[patent_app_number] => 10/887525
[patent_app_country] => US
[patent_app_date] => 2004-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 6015
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[patent_maintenance] => 1
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[pdf_file] => publications/A1/0010/20060010277.pdf
[firstpage_image] =>[orig_patent_app_number] => 10887525
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/887525 | Isolation of input/output adapter interrupt domains | Jul 7, 2004 | Abandoned |
Array
(
[id] => 7447217
[patent_doc_number] => 20040267881
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Automatic server-side plug-and-play without user intervention'
[patent_app_type] => new
[patent_app_number] => 10/885298
[patent_app_country] => US
[patent_app_date] => 2004-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0267/20040267881.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/885298 | Automatic server-side plug-and-play without user intervention | Jul 6, 2004 | Abandoned |
Array
(
[id] => 7063092
[patent_doc_number] => 20050005049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Method and data structure for random access via a bus connection'
[patent_app_type] => utility
[patent_app_number] => 10/882071
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/882071 | Method and data structure for random access via a bus connection | Jun 29, 2004 | Issued |
Array
(
[id] => 713168
[patent_doc_number] => 07062594
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-06-13
[patent_title] => 'Root complex connection system'
[patent_app_type] => utility
[patent_app_number] => 10/881553
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/881553 | Root complex connection system | Jun 29, 2004 | Issued |
Array
(
[id] => 7047016
[patent_doc_number] => 20050251611
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[patent_issue_date] => 2005-11-10
[patent_title] => 'Transmitting peer-to-peer transactions through a coherent interface'
[patent_app_type] => utility
[patent_app_number] => 10/832607
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[patent_app_date] => 2004-04-27
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10832607
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/832607 | Transmitting peer-to-peer transactions through a coherent interface | Apr 26, 2004 | Issued |
Array
(
[id] => 6953822
[patent_doc_number] => 20050228917
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[patent_issue_date] => 2005-10-13
[patent_title] => 'Novel structure and method for interrupt detection and processing'
[patent_app_type] => utility
[patent_app_number] => 10/813602
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2878
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[pdf_file] => publications/A1/0228/20050228917.pdf
[firstpage_image] =>[orig_patent_app_number] => 10813602
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/813602 | Novel structure and method for interrupt detection and processing | Mar 29, 2004 | Abandoned |
Array
(
[id] => 6962045
[patent_doc_number] => 20050216628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'PC CardBus structure'
[patent_app_type] => utility
[patent_app_number] => 10/809405
[patent_app_country] => US
[patent_app_date] => 2004-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1147
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[pdf_file] => publications/A1/0216/20050216628.pdf
[firstpage_image] =>[orig_patent_app_number] => 10809405
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/809405 | PC CardBus structure | Mar 25, 2004 | Issued |
Array
(
[id] => 704997
[patent_doc_number] => 07069371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Motherboard having a non-volatile memory which is reprogrammable through a video display port and a non-volatile memory switchable between two communication protocols'
[patent_app_type] => utility
[patent_app_number] => 10/798485
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[patent_app_date] => 2004-03-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/798485 | Motherboard having a non-volatile memory which is reprogrammable through a video display port and a non-volatile memory switchable between two communication protocols | Mar 9, 2004 | Issued |
Array
(
[id] => 469215
[patent_doc_number] => 07240135
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Method of balancing work load with prioritized tasks across a multitude of communication ports'
[patent_app_type] => utility
[patent_app_number] => 10/794377
[patent_app_country] => US
[patent_app_date] => 2004-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2792
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[pdf_file] => patents/07/240/07240135.pdf
[firstpage_image] =>[orig_patent_app_number] => 10794377
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/794377 | Method of balancing work load with prioritized tasks across a multitude of communication ports | Mar 4, 2004 | Issued |
Array
(
[id] => 6913909
[patent_doc_number] => 20050177667
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-11
[patent_title] => 'Interrupt priority control within a nested interrupt system'
[patent_app_type] => utility
[patent_app_number] => 10/775334
[patent_app_country] => US
[patent_app_date] => 2004-02-11
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[firstpage_image] =>[orig_patent_app_number] => 10775334
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/775334 | Interrupt priority control within a nested interrupt system | Feb 10, 2004 | Issued |
Array
(
[id] => 400512
[patent_doc_number] => 07296109
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[patent_issue_date] => 2007-11-13
[patent_title] => 'Buffer bypass circuit for reducing latency in information transfers to a bus'
[patent_app_type] => utility
[patent_app_number] => 10/767001
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[firstpage_image] =>[orig_patent_app_number] => 10767001
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/767001 | Buffer bypass circuit for reducing latency in information transfers to a bus | Jan 28, 2004 | Issued |
Array
(
[id] => 7476764
[patent_doc_number] => 20040122984
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[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'Data processor and data table update method'
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[patent_app_number] => 10/477400
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[firstpage_image] =>[orig_patent_app_number] => 10477400
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/477400 | Data processor and data table update method | Jan 19, 2004 | Abandoned |
Array
(
[id] => 6973777
[patent_doc_number] => 20050038949
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[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Apparatus for enabling distributed processing across a plurality of circuit cards'
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[patent_app_number] => 10/752428
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/752428 | Apparatus for enabling distributed processing across a plurality of circuit cards | Jan 5, 2004 | Abandoned |
Array
(
[id] => 739493
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[patent_title] => 'Selective smart discards with prefetchable and controlled-prefetchable address space'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/742185 | Selective smart discards with prefetchable and controlled-prefetchable address space | Dec 17, 2003 | Issued |
Array
(
[id] => 508000
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[patent_title] => 'Efficient connection between modules of removable electronic circuit cards'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/732149 | Efficient connection between modules of removable electronic circuit cards | Dec 8, 2003 | Issued |
Array
(
[id] => 7185225
[patent_doc_number] => 20050125582
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[patent_issue_date] => 2005-06-09
[patent_title] => 'Methods and apparatus to dispatch interrupts in multi-processor systems'
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Array
(
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/687128 | Bus control device and information processing system | Oct 14, 2003 | Issued |