Search

Christopher E. Lee

Examiner (ID: 4808)

Most Active Art Unit
3992
Art Unit(s)
2111, 2181, 2189, 2112, 3992
Total Applications
369
Issued Applications
281
Pending Applications
10
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 481232 [patent_doc_number] => 07228375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'System and method for efficient input/output of a computer system' [patent_app_type] => utility [patent_app_number] => 10/042971 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6607 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228375.pdf [firstpage_image] =>[orig_patent_app_number] => 10042971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042971
System and method for efficient input/output of a computer system Jan 6, 2002 Issued
Array ( [id] => 1218112 [patent_doc_number] => 06711643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method and apparatus for interrupt redirection for arm processors' [patent_app_type] => B2 [patent_app_number] => 10/028702 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4457 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 513 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711643.pdf [firstpage_image] =>[orig_patent_app_number] => 10028702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028702
Method and apparatus for interrupt redirection for arm processors Dec 27, 2001 Issued
Array ( [id] => 1360983 [patent_doc_number] => 06587902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'I/O port assembly of notebook computer connectable to monitor or TV as needed' [patent_app_type] => B1 [patent_app_number] => 10/026648 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2684 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587902.pdf [firstpage_image] =>[orig_patent_app_number] => 10026648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026648
I/O port assembly of notebook computer connectable to monitor or TV as needed Dec 26, 2001 Issued
Array ( [id] => 6667602 [patent_doc_number] => 20030112585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Multiprocessor notebook computer with a tablet PC conversion capability' [patent_app_type] => new [patent_app_number] => 10/020717 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112585.pdf [firstpage_image] =>[orig_patent_app_number] => 10020717 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020717
Multiprocessor notebook computer with a tablet PC conversion capability Dec 12, 2001 Abandoned
Array ( [id] => 5990613 [patent_doc_number] => 20020099890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Apparatus and method for processing interruptions in a data transmission over a bus' [patent_app_type] => new [patent_app_number] => 09/989317 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4672 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099890.pdf [firstpage_image] =>[orig_patent_app_number] => 09989317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989317
Apparatus and method for processing interruptions in a data transmission over a bus Nov 19, 2001 Abandoned
Array ( [id] => 6862600 [patent_doc_number] => 20030093608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Method for increasing peripheral component interconnect (PCI) bus thoughput via a bridge for memory read transfers via dynamic variable prefetch' [patent_app_type] => new [patent_app_number] => 10/039707 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20030093608.pdf [firstpage_image] =>[orig_patent_app_number] => 10039707 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039707
Method for increasing peripheral component interconnect (PCI) bus thoughput via a bridge for memory read transfers via dynamic variable prefetch Nov 8, 2001 Abandoned
Array ( [id] => 6294094 [patent_doc_number] => 20020055984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Method for device-to-device pervasive digital output' [patent_app_type] => new [patent_app_number] => 10/016630 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16916 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055984.pdf [firstpage_image] =>[orig_patent_app_number] => 10016630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016630
Method for device-to-device pervasive digital output Oct 31, 2001 Abandoned
Array ( [id] => 1124756 [patent_doc_number] => 06799234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Apparatus and method for randomly assigning slots in a PCI backplane' [patent_app_type] => B1 [patent_app_number] => 10/035553 [patent_app_country] => US [patent_app_date] => 2001-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2291 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799234.pdf [firstpage_image] =>[orig_patent_app_number] => 10035553 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035553
Apparatus and method for randomly assigning slots in a PCI backplane Oct 26, 2001 Issued
Array ( [id] => 1020869 [patent_doc_number] => 06892258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Hardware semaphores for a multi-processor system within a shared memory architecture' [patent_app_type] => utility [patent_app_number] => 10/015076 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3998 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892258.pdf [firstpage_image] =>[orig_patent_app_number] => 10015076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015076
Hardware semaphores for a multi-processor system within a shared memory architecture Oct 25, 2001 Issued
Array ( [id] => 6306906 [patent_doc_number] => 20020094704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Arrangement for the identification of the logical composition of a modular system' [patent_app_type] => new [patent_app_number] => 10/000519 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2630 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094704.pdf [firstpage_image] =>[orig_patent_app_number] => 10000519 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000519
Arrangement for the identification of the logical composition of a modular system Oct 22, 2001 Abandoned
Array ( [id] => 6661034 [patent_doc_number] => 20030135678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Two level multi-tier system bus' [patent_app_type] => new [patent_app_number] => 09/955961 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 24121 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135678.pdf [firstpage_image] =>[orig_patent_app_number] => 09955961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955961
Two level multi-tier system bus Sep 19, 2001 Issued
09/936909 Digital signal transmission system for building systems engineering Sep 18, 2001 Abandoned
Array ( [id] => 1001675 [patent_doc_number] => 06912613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Apparatus and method for connecting base module and function-extending module in AV system' [patent_app_type] => utility [patent_app_number] => 09/955301 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5251 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912613.pdf [firstpage_image] =>[orig_patent_app_number] => 09955301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955301
Apparatus and method for connecting base module and function-extending module in AV system Sep 18, 2001 Issued
Array ( [id] => 6775504 [patent_doc_number] => 20030018842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Interrupt controller' [patent_app_type] => new [patent_app_number] => 09/908770 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4433 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018842.pdf [firstpage_image] =>[orig_patent_app_number] => 09908770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908770
Interrupt controller Jul 18, 2001 Abandoned
Array ( [id] => 6775502 [patent_doc_number] => 20030018840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Power bus information transmission system and method of data transmission' [patent_app_type] => new [patent_app_number] => 09/908104 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3667 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018840.pdf [firstpage_image] =>[orig_patent_app_number] => 09908104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908104
Power bus information transmission system and method of data transmission Jul 17, 2001 Abandoned
Array ( [id] => 6693765 [patent_doc_number] => 20030041197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method and apparatus for position dependent data scheduling' [patent_app_type] => new [patent_app_number] => 09/906900 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9212 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20030041197.pdf [firstpage_image] =>[orig_patent_app_number] => 09906900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906900
Method and apparatus for position dependent data scheduling Jul 15, 2001 Issued
Array ( [id] => 7321115 [patent_doc_number] => 20040225782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'METHOD FOR GENERATING CONFIGURATION TABLES AND FOR FORWARDING PACKETS THROUGH A NETWORK' [patent_app_type] => new [patent_app_number] => 09/905516 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5675 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225782.pdf [firstpage_image] =>[orig_patent_app_number] => 09905516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905516
Method for generating configuration tables and for forwarding packets through a network Jul 12, 2001 Issued
Array ( [id] => 6736944 [patent_doc_number] => 20030014579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Communication controller and method of transforming information' [patent_app_type] => new [patent_app_number] => 09/903178 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014579.pdf [firstpage_image] =>[orig_patent_app_number] => 09903178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903178
Communication controller and method of transforming information Jul 10, 2001 Abandoned
Array ( [id] => 6035497 [patent_doc_number] => 20020019898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Microprocessor, semiconductor module and data processing system' [patent_app_type] => new [patent_app_number] => 09/897902 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10593 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019898.pdf [firstpage_image] =>[orig_patent_app_number] => 09897902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897902
Microprocessor, semiconductor module and data processing system Jul 4, 2001 Abandoned
Array ( [id] => 6181224 [patent_doc_number] => 20020156958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method and chipset for system management mode interrupt of multi-processor supporting system' [patent_app_type] => new [patent_app_number] => 09/878882 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3325 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156958.pdf [firstpage_image] =>[orig_patent_app_number] => 09878882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878882
Method and chipset for system management mode interrupt of multi-processor supporting system Jun 10, 2001 Issued
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