Christopher E. Lee

Array ( [id] => 940393 [patent_doc_number] => 06973523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Code division multiple access modem interface' [patent_app_type] => utility [patent_app_number] => 09/699145 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3240 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973523.pdf [firstpage_image] =>[orig_patent_app_number] => 09699145 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771280 [patent_doc_number] => 07010636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method and apparatus for rapid data transfer between dis-similar devices' [patent_app_type] => utility [patent_app_number] => 09/675974 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1592 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010636.pdf [firstpage_image] =>[orig_patent_app_number] => 09675974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1039974 [patent_doc_number] => 06874052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Expansion bridge apparatus and method for an I2C bus' [patent_app_type] => utility [patent_app_number] => 09/677061 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 13072 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/874/06874052.pdf [firstpage_image] =>[orig_patent_app_number] => 09677061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297971 [patent_doc_number] => 06631433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Bus arbiter for a data storage system' [patent_app_type] => B1 [patent_app_number] => 09/670709 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 43 [patent_no_of_words] => 24827 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631433.pdf [firstpage_image] =>[orig_patent_app_number] => 09670709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 933280 [patent_doc_number] => 06981076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Mechanism to disable dynamically a computer audio input/output connector' [patent_app_type] => utility [patent_app_number] => 09/672131 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2520 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981076.pdf [firstpage_image] =>[orig_patent_app_number] => 09672131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1007677 [patent_doc_number] => 06907488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Serial data transmission via a bus system' [patent_app_type] => utility [patent_app_number] => 10/070991 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6750 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907488.pdf [firstpage_image] =>[orig_patent_app_number] => 10070991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1221686 [patent_doc_number] => 06708242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Methods for addressing extended number of peripheral devices over peripheral bus' [patent_app_type] => B1 [patent_app_number] => 09/636038 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708242.pdf [firstpage_image] =>[orig_patent_app_number] => 09636038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 940390 [patent_doc_number] => 06973522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Microcomputer with program-revision ability' [patent_app_type] => utility [patent_app_number] => 09/635524 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 23469 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973522.pdf [firstpage_image] =>[orig_patent_app_number] => 09635524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180875 [patent_doc_number] => 06754761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Communications system including symmetric bus bridge and method used therewith' [patent_app_type] => B1 [patent_app_number] => 09/633856 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4848 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754761.pdf [firstpage_image] =>[orig_patent_app_number] => 09633856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 953214 [patent_doc_number] => 06961785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'Permanent open firmware PCI host bridge (PHB) unit addressing to support dynamic memory mapping and swapping of I/O drawers' [patent_app_type] => utility [patent_app_number] => 09/631723 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4444 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961785.pdf [firstpage_image] =>[orig_patent_app_number] => 09631723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1356785 [patent_doc_number] => 06591322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and apparatus for connecting single master devices to a multimaster wired-and bus environment' [patent_app_type] => B1 [patent_app_number] => 09/630099 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13406 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591322.pdf [firstpage_image] =>[orig_patent_app_number] => 09630099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429677 [patent_doc_number] => 06510479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Transmit pre-arbitration scheme for a can device and a can device that implements this scheme' [patent_app_type] => B1 [patent_app_number] => 09/630642 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10466 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510479.pdf [firstpage_image] =>[orig_patent_app_number] => 09630642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7610045 [patent_doc_number] => 06842814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method for managing a digital interface connection' [patent_app_type] => utility [patent_app_number] => 09/626078 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3620 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842814.pdf [firstpage_image] =>[orig_patent_app_number] => 09626078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1186322 [patent_doc_number] => 06742071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Real-time I/O processor used to implement bus interface protocols' [patent_app_type] => B1 [patent_app_number] => 09/625167 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6417 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742071.pdf [firstpage_image] =>[orig_patent_app_number] => 09625167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1177390 [patent_doc_number] => 06760798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Interface mechanism and method for interfacing a real-time clock with a data processing circuit' [patent_app_type] => B1 [patent_app_number] => 09/616067 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6286 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760798.pdf [firstpage_image] =>[orig_patent_app_number] => 09616067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1284430 [patent_doc_number] => 06651129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Apparatus and method for establishing a data communication interface to control and configure an electronic system with analog and digital circuits' [patent_app_type] => B1 [patent_app_number] => 09/614081 [patent_app_country] => US [patent_app_date] => 2000-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6590 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651129.pdf [firstpage_image] =>[orig_patent_app_number] => 09614081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959932 [patent_doc_number] => 06954814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-11 [patent_title] => 'Method and system for monitoring and transmitting utility status via universal communications interface' [patent_app_type] => utility [patent_app_number] => 09/591258 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2626 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954814.pdf [firstpage_image] =>[orig_patent_app_number] => 09591258 [rel_patent_id] =>[rel_patent_doc_number] =>)