Christopher K Moore

Array ( [id] => 1434077 [patent_doc_number] => 06341367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Hardware realized state machine' [patent_app_type] => B1 [patent_app_number] => 09/624932 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3645 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341367.pdf [firstpage_image] =>[orig_patent_app_number] => 09624932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4371916 [patent_doc_number] => 06216257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks' [patent_app_type] => 1 [patent_app_number] => 9/603807 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 22094 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216257.pdf [firstpage_image] =>[orig_patent_app_number] => 603807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7638545 [patent_doc_number] => 06397376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and apparatus for determining wiring route in circuit board and information storage medium' [patent_app_type] => B1 [patent_app_number] => 09/462837 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 89 [patent_no_of_words] => 24163 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397376.pdf [firstpage_image] =>[orig_patent_app_number] => 09462837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1490359 [patent_doc_number] => 06367054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method of generating finite state data for designing a cascade decomposed logic circuit' [patent_app_type] => B1 [patent_app_number] => 09/406941 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 19148 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367054.pdf [firstpage_image] =>[orig_patent_app_number] => 09406941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1434075 [patent_doc_number] => 06341365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method for automating the placement of a repeater device in an optimal location, considering pre-defined blockages, in high frequency very large scale integration/ultra large scale integration (VLSI/ULSI) electronic designs' [patent_app_type] => B1 [patent_app_number] => 09/396327 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2816 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341365.pdf [firstpage_image] =>[orig_patent_app_number] => 09396327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1526632 [patent_doc_number] => 06353922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Automatic generation of one dimensional data compaction commands for electron beam lithography' [patent_app_type] => B1 [patent_app_number] => 09/382107 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5120 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353922.pdf [firstpage_image] =>[orig_patent_app_number] => 09382107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423842 [patent_doc_number] => 06311311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test' [patent_app_type] => 1 [patent_app_number] => 9/377125 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2254 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311311.pdf [firstpage_image] =>[orig_patent_app_number] => 377125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4333960 [patent_doc_number] => 06317862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Modular preamplifier head circuit layout' [patent_app_type] => 1 [patent_app_number] => 9/375828 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4513 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317862.pdf [firstpage_image] =>[orig_patent_app_number] => 375828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291283 [patent_doc_number] => 06308309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Place-holding library elements for defining routing paths' [patent_app_type] => 1 [patent_app_number] => 9/374254 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4696 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308309.pdf [firstpage_image] =>[orig_patent_app_number] => 374254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1526610 [patent_doc_number] => 06353918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Interconnection routing system' [patent_app_type] => B1 [patent_app_number] => 09/142793 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 49 [patent_no_of_words] => 10814 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353918.pdf [firstpage_image] =>[orig_patent_app_number] => 09142793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4295405 [patent_doc_number] => 06324673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method and apparatus for edge-endpoint-based VLSI design rule checking' [patent_app_type] => 1 [patent_app_number] => 9/321591 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 10496 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324673.pdf [firstpage_image] =>[orig_patent_app_number] => 321591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305393 [patent_doc_number] => 06269470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Efficient routing of conductors between datapaths' [patent_app_type] => 1 [patent_app_number] => 9/321479 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1837 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269470.pdf [firstpage_image] =>[orig_patent_app_number] => 321479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1452529 [patent_doc_number] => 06370676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'On-demand process sorting method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/321048 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2828 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370676.pdf [firstpage_image] =>[orig_patent_app_number] => 09321048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4399940 [patent_doc_number] => 06295632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'System and method for detecting the output of a clock driver' [patent_app_type] => 1 [patent_app_number] => 9/311314 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8925 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295632.pdf [firstpage_image] =>[orig_patent_app_number] => 311314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4325297 [patent_doc_number] => 06327693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Interconnect delay driven placement and routing of an integrated circuit design' [patent_app_type] => 1 [patent_app_number] => 9/290013 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3741 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327693.pdf [firstpage_image] =>[orig_patent_app_number] => 290013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424455 [patent_doc_number] => 06301696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template' [patent_app_type] => 1 [patent_app_number] => 9/281008 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 8003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301696.pdf [firstpage_image] =>[orig_patent_app_number] => 281008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444057 [patent_doc_number] => 06336209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Information processing system that processes portions of an application program using programmable logic circuits' [patent_app_type] => B1 [patent_app_number] => 09/280681 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 15146 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336209.pdf [firstpage_image] =>[orig_patent_app_number] => 09280681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4382176 [patent_doc_number] => 06256767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)' [patent_app_type] => 1 [patent_app_number] => 9/282049 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7239 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256767.pdf [firstpage_image] =>[orig_patent_app_number] => 282049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4281782 [patent_doc_number] => 06260178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Component placement machine step size determination for improved throughput via an evolutionary algorithm' [patent_app_type] => 1 [patent_app_number] => 9/277636 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5904 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260178.pdf [firstpage_image] =>[orig_patent_app_number] => 277636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1481394 [patent_doc_number] => 06389577 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Analyzing CMOS circuit delay' [patent_app_type] => B1 [patent_app_number] => 09/276389 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389577.pdf [firstpage_image] =>[orig_patent_app_number] => 09276389 [rel_patent_id] =>[rel_patent_doc_number] =>)