Christopher L. Templeton

Array ( [id] => 4018902 [patent_doc_number] => 05889682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Clock routing design method using a hieraichical layout design' [patent_app_type] => 1 [patent_app_number] => 8/951480 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 10024 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889682.pdf [firstpage_image] =>[orig_patent_app_number] => 951480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054177 [patent_doc_number] => 05912824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Ion implantation simulation method' [patent_app_type] => 1 [patent_app_number] => 8/932642 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3717 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912824.pdf [firstpage_image] =>[orig_patent_app_number] => 932642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4034236 [patent_doc_number] => 05926403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method and system for concurrent computing between heterogeneous simulators' [patent_app_type] => 1 [patent_app_number] => 8/861849 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9293 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926403.pdf [firstpage_image] =>[orig_patent_app_number] => 861849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3897647 [patent_doc_number] => 05805866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Alignment method' [patent_app_type] => 1 [patent_app_number] => 8/826064 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 11991 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805866.pdf [firstpage_image] =>[orig_patent_app_number] => 826064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131482 [patent_doc_number] => 06062715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Computer implemented aircraft simulation method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/821434 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1231 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/062/06062715.pdf [firstpage_image] =>[orig_patent_app_number] => 821434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788853 [patent_doc_number] => 05808917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Synthesis of low power linear digital signal processing circuits using activity metrics' [patent_app_type] => 1 [patent_app_number] => 8/818084 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808917.pdf [firstpage_image] =>[orig_patent_app_number] => 818084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4030114 [patent_doc_number] => 05907698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method and apparatus for characterizing static and dynamic operation of an architectural system' [patent_app_type] => 1 [patent_app_number] => 8/805099 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10724 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907698.pdf [firstpage_image] =>[orig_patent_app_number] => 805099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3782752 [patent_doc_number] => 05850537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation' [patent_app_type] => 1 [patent_app_number] => 8/806542 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 8649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850537.pdf [firstpage_image] =>[orig_patent_app_number] => 806542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3802018 [patent_doc_number] => 05841678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Modeling and simulation of a reaction for hydrotreating hydrocarbon oil' [patent_app_type] => 1 [patent_app_number] => 8/785467 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8012 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841678.pdf [firstpage_image] =>[orig_patent_app_number] => 785467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882581 [patent_doc_number] => 05838595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Apparatus and method for model based process control' [patent_app_type] => 1 [patent_app_number] => 8/755689 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838595.pdf [firstpage_image] =>[orig_patent_app_number] => 755689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4068724 [patent_doc_number] => 05970237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Device to assist software emulation of hardware functions' [patent_app_type] => 1 [patent_app_number] => 8/752153 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2795 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970237.pdf [firstpage_image] =>[orig_patent_app_number] => 752153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036613 [patent_doc_number] => 05883807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Schematic synthesizer' [patent_app_type] => 1 [patent_app_number] => 8/730926 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7192 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883807.pdf [firstpage_image] =>[orig_patent_app_number] => 730926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891633 [patent_doc_number] => 05805470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Verification of instruction and data fetch resources in a functional model of a speculative out-of order computer system' [patent_app_type] => 1 [patent_app_number] => 8/728468 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805470.pdf [firstpage_image] =>[orig_patent_app_number] => 728468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3791675 [patent_doc_number] => 05818736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'System and method for simulating signal flow through a logic block pattern of a real time process control system' [patent_app_type] => 1 [patent_app_number] => 8/725005 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818736.pdf [firstpage_image] =>[orig_patent_app_number] => 725005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873287 [patent_doc_number] => 05793648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method and system for automating control panel layout and wiring specifications for a vehicle manufacturing process' [patent_app_type] => 1 [patent_app_number] => 8/724730 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793648.pdf [firstpage_image] =>[orig_patent_app_number] => 724730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849543 [patent_doc_number] => 05815687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Apparatus and method for simulating domino logic circuits using a special machine cycle to validate pre-charge' [patent_app_type] => 1 [patent_app_number] => 8/715729 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5559 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815687.pdf [firstpage_image] =>[orig_patent_app_number] => 715729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891458 [patent_doc_number] => 05798949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Traffic safety prediction model' [patent_app_type] => 1 [patent_app_number] => 8/689651 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 21007 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798949.pdf [firstpage_image] =>[orig_patent_app_number] => 689651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4030099 [patent_doc_number] => 05907697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network' [patent_app_type] => 1 [patent_app_number] => 8/688329 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907697.pdf [firstpage_image] =>[orig_patent_app_number] => 688329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4164734 [patent_doc_number] => 06036349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method and apparatus for validation of model-based predictions' [patent_app_type] => 1 [patent_app_number] => 8/687726 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 16 [patent_no_of_words] => 4224 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/036/06036349.pdf [firstpage_image] =>[orig_patent_app_number] => 687726 [rel_patent_id] =>[rel_patent_doc_number] =>)