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Christopher Lee

Examiner (ID: 16167)

Most Active Art Unit
2916
Art Unit(s)
2916
Total Applications
855
Issued Applications
847
Pending Applications
0
Abandoned Applications
8

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4155830 [patent_doc_number] => 06114253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Via patterning for poly(arylene ether) used as an inter-metal dielectric' [patent_app_type] => 1 [patent_app_number] => 9/268542 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3225 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114253.pdf [firstpage_image] =>[orig_patent_app_number] => 268542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268542
Via patterning for poly(arylene ether) used as an inter-metal dielectric Mar 14, 1999 Issued
Array ( [id] => 4351306 [patent_doc_number] => 06291360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method of etching a layer' [patent_app_type] => 1 [patent_app_number] => 9/265784 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2514 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291360.pdf [firstpage_image] =>[orig_patent_app_number] => 265784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265784
Method of etching a layer Mar 9, 1999 Issued
09/261786 METHOD AND SYSTEM TO UNIFORMLY ETCH SUBSTRATES USING AN ETCHING COMPOSITION COMPRISING A FLUORIDE ION SOURCE AND A HYDROGEN ION SOURCE Mar 2, 1999 Abandoned
Array ( [id] => 4234290 [patent_doc_number] => 06074948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for manufacturing thin semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/252978 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 3733 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074948.pdf [firstpage_image] =>[orig_patent_app_number] => 252978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252978
Method for manufacturing thin semiconductor device Feb 18, 1999 Issued
Array ( [id] => 4173167 [patent_doc_number] => 06083842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug' [patent_app_type] => 1 [patent_app_number] => 9/253479 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3288 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083842.pdf [firstpage_image] =>[orig_patent_app_number] => 253479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253479
Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug Feb 18, 1999 Issued
09/251588 MASKING METHODS AND ETCHING SEQUENCES FOR PATTERNING ELECTRODES OF HIGH DENSITY RAM CAPACITORS Feb 16, 1999 Abandoned
Array ( [id] => 4271723 [patent_doc_number] => 06323132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Etching methods for anisotropic platinum profile' [patent_app_type] => 1 [patent_app_number] => 9/251826 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 26370 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323132.pdf [firstpage_image] =>[orig_patent_app_number] => 251826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251826
Etching methods for anisotropic platinum profile Feb 16, 1999 Issued
Array ( [id] => 1440375 [patent_doc_number] => 06334928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor processing system and method of using the same' [patent_app_type] => B1 [patent_app_number] => 09/239793 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5044 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334928.pdf [firstpage_image] =>[orig_patent_app_number] => 09239793 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239793
Semiconductor processing system and method of using the same Jan 28, 1999 Issued
Array ( [id] => 4236078 [patent_doc_number] => 06165906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor topography employing a shallow trench isolation structure with an improved trench edge' [patent_app_type] => 1 [patent_app_number] => 9/237412 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165906.pdf [firstpage_image] =>[orig_patent_app_number] => 237412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237412
Semiconductor topography employing a shallow trench isolation structure with an improved trench edge Jan 25, 1999 Issued
Array ( [id] => 7640279 [patent_doc_number] => 06395635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Reduction of tungsten damascene residue' [patent_app_type] => B1 [patent_app_number] => 09/206741 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2505 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395635.pdf [firstpage_image] =>[orig_patent_app_number] => 09206741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206741
Reduction of tungsten damascene residue Dec 6, 1998 Issued
09/201589 METHOD FOR REMOVING REDEPOSITED VEILS FROM ETCHED PLATINUM Nov 29, 1998 Abandoned
09/201588 METHOD FOR REMOVING REDEPOSITED VEILS FROM ETCHED PLATINUM Nov 29, 1998 Abandoned
Array ( [id] => 7118465 [patent_doc_number] => 20010001745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'CRYSTALLIZATION PROCESSING OF SEMICONDUCTOR FILM REGIONS ON A SUBSTRATE, AND DEVICES MADE THEREWITH' [patent_app_type] => new-utility [patent_app_number] => 09/200533 [patent_app_country] => US [patent_app_date] => 1998-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4010 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001745.pdf [firstpage_image] =>[orig_patent_app_number] => 09200533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200533
Crystallization processing of semiconductor film regions on a substrate, and devices made therewith Nov 26, 1998 Issued
Array ( [id] => 4156466 [patent_doc_number] => 06156659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Linear CMP tool design with closed loop slurry distribution' [patent_app_type] => 1 [patent_app_number] => 9/195655 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1997 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156659.pdf [firstpage_image] =>[orig_patent_app_number] => 195655 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195655
Linear CMP tool design with closed loop slurry distribution Nov 18, 1998 Issued
Array ( [id] => 4290338 [patent_doc_number] => 06235635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Linear CMP tool design using in-situ slurry distribution and concurrent pad conditioning' [patent_app_type] => 1 [patent_app_number] => 9/195654 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2858 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235635.pdf [firstpage_image] =>[orig_patent_app_number] => 195654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195654
Linear CMP tool design using in-situ slurry distribution and concurrent pad conditioning Nov 18, 1998 Issued
Array ( [id] => 4205381 [patent_doc_number] => 06077785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Ultrasonic processing of chemical mechanical polishing slurries' [patent_app_type] => 1 [patent_app_number] => 9/190086 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3777 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077785.pdf [firstpage_image] =>[orig_patent_app_number] => 190086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190086
Ultrasonic processing of chemical mechanical polishing slurries Nov 11, 1998 Issued
Array ( [id] => 4003303 [patent_doc_number] => 06004883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Dual damascene patterned conductor layer formation method without etch stop layer' [patent_app_type] => 1 [patent_app_number] => 9/177186 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7045 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004883.pdf [firstpage_image] =>[orig_patent_app_number] => 177186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177186
Dual damascene patterned conductor layer formation method without etch stop layer Oct 22, 1998 Issued
Array ( [id] => 4351173 [patent_doc_number] => 06291352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/167819 [patent_app_country] => US [patent_app_date] => 1998-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2780 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291352.pdf [firstpage_image] =>[orig_patent_app_number] => 167819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167819
Method of manufacturing a semiconductor device Oct 6, 1998 Issued
Array ( [id] => 4405419 [patent_doc_number] => 06271140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Coaxial dressing for chemical mechanical polishing' [patent_app_type] => 1 [patent_app_number] => 9/165001 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2548 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271140.pdf [firstpage_image] =>[orig_patent_app_number] => 165001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165001
Coaxial dressing for chemical mechanical polishing Sep 30, 1998 Issued
Array ( [id] => 1507502 [patent_doc_number] => 06440859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method for etching passivation layer of wafer' [patent_app_type] => B1 [patent_app_number] => 09/160964 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1324 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440859.pdf [firstpage_image] =>[orig_patent_app_number] => 09160964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160964
Method for etching passivation layer of wafer Sep 24, 1998 Issued
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