Christopher M Gross
Examiner (ID: 1514, Phone: (571)272-4446 , Office: P/1639 )
Most Active Art Unit | 1639 |
Art Unit(s) | 1639, 1675, 1636 |
Total Applications | 858 |
Issued Applications | 439 |
Pending Applications | 102 |
Abandoned Applications | 317 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 8691567
[patent_doc_number] => 08391098
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-05
[patent_title] => 'Data input/output circuit and method of semiconductor memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/154622
[patent_app_country] => US
[patent_app_date] => 2011-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5551
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13154622
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/154622 | Data input/output circuit and method of semiconductor memory apparatus | Jun 6, 2011 | Issued |
Array
(
[id] => 9101135
[patent_doc_number] => 08565024
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-22
[patent_title] => 'Sensing memory cells'
[patent_app_type] => utility
[patent_app_number] => 13/114640
[patent_app_country] => US
[patent_app_date] => 2011-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7712
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13114640
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/114640 | Sensing memory cells | May 23, 2011 | Issued |
Array
(
[id] => 8399847
[patent_doc_number] => 08270234
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-09-18
[patent_title] => 'Positive and negative voltage level shifter circuit'
[patent_app_type] => utility
[patent_app_number] => 13/113303
[patent_app_country] => US
[patent_app_date] => 2011-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 6577
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13113303
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/113303 | Positive and negative voltage level shifter circuit | May 22, 2011 | Issued |
Array
(
[id] => 8482042
[patent_doc_number] => 20120281450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'ELECTRICALLY PROGRAMMABLE FUSE MODULE IN SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/102061
[patent_app_country] => US
[patent_app_date] => 2011-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3468
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102061
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/102061 | Electrically programmable fuse module in semiconductor device | May 5, 2011 | Issued |
Array
(
[id] => 9075892
[patent_doc_number] => 08553477
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-08
[patent_title] => 'Data interface circuit, nonvolatile memory device including the same and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/102823
[patent_app_country] => US
[patent_app_date] => 2011-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3470
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102823
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/102823 | Data interface circuit, nonvolatile memory device including the same and operating method thereof | May 5, 2011 | Issued |
Array
(
[id] => 9128682
[patent_doc_number] => 08576638
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Non-volatile memory device and non-volatile memory system having the same'
[patent_app_type] => utility
[patent_app_number] => 13/095159
[patent_app_country] => US
[patent_app_date] => 2011-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 18053
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13095159
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/095159 | Non-volatile memory device and non-volatile memory system having the same | Apr 26, 2011 | Issued |
Array
(
[id] => 7498198
[patent_doc_number] => 20110261638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-27
[patent_title] => 'Method for Storing Data into a Memory'
[patent_app_type] => utility
[patent_app_number] => 13/091433
[patent_app_country] => US
[patent_app_date] => 2011-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3748
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20110261638.pdf
[firstpage_image] =>[orig_patent_app_number] => 13091433
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/091433 | Method for storing data into a memory | Apr 20, 2011 | Issued |
Array
(
[id] => 6163473
[patent_doc_number] => 20110194368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-11
[patent_title] => 'Regulator and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/064817
[patent_app_country] => US
[patent_app_date] => 2011-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10464
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20110194368.pdf
[firstpage_image] =>[orig_patent_app_number] => 13064817
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/064817 | Regulator and semiconductor device | Apr 17, 2011 | Abandoned |
Array
(
[id] => 8835913
[patent_doc_number] => 08451678
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-28
[patent_title] => 'Semiconductor device including internal voltage generation circuit'
[patent_app_type] => utility
[patent_app_number] => 13/080114
[patent_app_country] => US
[patent_app_date] => 2011-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 29
[patent_no_of_words] => 11201
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080114
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/080114 | Semiconductor device including internal voltage generation circuit | Apr 4, 2011 | Issued |
Array
(
[id] => 8428567
[patent_doc_number] => 20120250442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-04
[patent_title] => 'Methods For Accessing DRAM Cells Using Separate Bit Line Control'
[patent_app_type] => utility
[patent_app_number] => 13/077811
[patent_app_country] => US
[patent_app_date] => 2011-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 12554
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077811
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/077811 | Methods for accessing DRAM cells using separate bit line control | Mar 30, 2011 | Issued |
Array
(
[id] => 8428565
[patent_doc_number] => 20120250440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-04
[patent_title] => 'Differential read write back sense amplifier circuits and methods'
[patent_app_type] => utility
[patent_app_number] => 13/076039
[patent_app_country] => US
[patent_app_date] => 2011-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6442
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13076039
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/076039 | Differential read write back sense amplifier circuits and methods | Mar 29, 2011 | Issued |
Array
(
[id] => 8415800
[patent_doc_number] => 20120243300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-27
[patent_title] => 'COMBINED DATA LEVEL-SHIFTER AND DE-SKEWER'
[patent_app_type] => utility
[patent_app_number] => 13/072375
[patent_app_country] => US
[patent_app_date] => 2011-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4403
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13072375
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/072375 | Combined data level-shifter and DE-skewer | Mar 24, 2011 | Issued |
Array
(
[id] => 7485117
[patent_doc_number] => 20110235415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND DATA STORAGE SYSTEM USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/070347
[patent_app_country] => US
[patent_app_date] => 2011-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20110235415.pdf
[firstpage_image] =>[orig_patent_app_number] => 13070347
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/070347 | Read method for nonvolatile memory device, and data storage system using the same | Mar 22, 2011 | Issued |
Array
(
[id] => 6086600
[patent_doc_number] => 20110216580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-08
[patent_title] => 'MRAM-BASED MEMORY DEVICE WITH ROTATED GATE'
[patent_app_type] => utility
[patent_app_number] => 13/038473
[patent_app_country] => US
[patent_app_date] => 2011-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4150
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20110216580.pdf
[firstpage_image] =>[orig_patent_app_number] => 13038473
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/038473 | MRAM-based memory device with rotated gate | Mar 1, 2011 | Issued |
Array
(
[id] => 5966917
[patent_doc_number] => 20110149672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-23
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/037779
[patent_app_country] => US
[patent_app_date] => 2011-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 4689
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20110149672.pdf
[firstpage_image] =>[orig_patent_app_number] => 13037779
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/037779 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | Feb 28, 2011 | Abandoned |
Array
(
[id] => 8369415
[patent_doc_number] => 20120218807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'RESISTIVE MEMORY SENSING METHODS AND DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/035193
[patent_app_country] => US
[patent_app_date] => 2011-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9279
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13035193
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/035193 | Resistive memory sensing methods and devices | Feb 24, 2011 | Issued |
Array
(
[id] => 6044820
[patent_doc_number] => 20110205812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/031073
[patent_app_country] => US
[patent_app_date] => 2011-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10878
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20110205812.pdf
[firstpage_image] =>[orig_patent_app_number] => 13031073
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/031073 | Semiconductor device | Feb 17, 2011 | Issued |
Array
(
[id] => 8068221
[patent_doc_number] => 20110242912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-06
[patent_title] => 'Random Access Memory Devices Having Word Line Drivers Therein That Support Variable-Frequency Clock Signals'
[patent_app_type] => utility
[patent_app_number] => 13/018539
[patent_app_country] => US
[patent_app_date] => 2011-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5783
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20110242912.pdf
[firstpage_image] =>[orig_patent_app_number] => 13018539
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/018539 | Random access memory devices having word line drivers therein that support variable-frequency clock signals | Jan 31, 2011 | Issued |
Array
(
[id] => 9141890
[patent_doc_number] => 08582363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-12
[patent_title] => 'Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory'
[patent_app_type] => utility
[patent_app_number] => 12/931395
[patent_app_country] => US
[patent_app_date] => 2011-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 20831
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 604
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12931395
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/931395 | Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory | Jan 30, 2011 | Issued |
Array
(
[id] => 6181036
[patent_doc_number] => 20110122699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-26
[patent_title] => 'CONTROLLING A MEMORY DEVICE RESPONSIVE TO DEGRADATION'
[patent_app_type] => utility
[patent_app_number] => 13/015457
[patent_app_country] => US
[patent_app_date] => 2011-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4197
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20110122699.pdf
[firstpage_image] =>[orig_patent_app_number] => 13015457
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/015457 | Controlling a memory device responsive to degradation | Jan 26, 2011 | Issued |