Christopher M Gross
Examiner (ID: 1514, Phone: (571)272-4446 , Office: P/1639 )
Most Active Art Unit | 1639 |
Art Unit(s) | 1639, 1675, 1636 |
Total Applications | 858 |
Issued Applications | 439 |
Pending Applications | 102 |
Abandoned Applications | 317 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 8314910
[patent_doc_number] => 20120191923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-26
[patent_title] => 'OUTPUTTING A PARTICULAR DATA QUANTIZATION FROM MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/010589
[patent_app_country] => US
[patent_app_date] => 2011-01-20
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13010589
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/010589 | Outputting a particular data quantization from memory | Jan 19, 2011 | Issued |
Array
(
[id] => 6044801
[patent_doc_number] => 20110205796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'NONVOLATILE MEMORY DEVICE AND SYSTEM PERFORMING REPAIR OPERATION FOR DEFECTIVE MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 13/008431
[patent_app_country] => US
[patent_app_date] => 2011-01-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0205/20110205796.pdf
[firstpage_image] =>[orig_patent_app_number] => 13008431
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/008431 | Nonvolatile memory device and system performing repair operation for defective memory cell | Jan 17, 2011 | Issued |
Array
(
[id] => 8803560
[patent_doc_number] => 08441840
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Semiconductor device and data processing system'
[patent_app_type] => utility
[patent_app_number] => 13/006109
[patent_app_country] => US
[patent_app_date] => 2011-01-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/006109 | Semiconductor device and data processing system | Jan 12, 2011 | Issued |
Array
(
[id] => 8288525
[patent_doc_number] => 20120176850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-12
[patent_title] => 'COLUMN ADDRESS STROBE WRITE LATENCY (CWL) CALIBRATION IN A MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/985481
[patent_app_country] => US
[patent_app_date] => 2011-01-06
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985481
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/985481 | Column address strobe write latency (CWL) calibration in a memory system | Jan 5, 2011 | Issued |
Array
(
[id] => 8544867
[patent_doc_number] => 08320164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-27
[patent_title] => 'Static random access memory with data controlled power supply'
[patent_app_type] => utility
[patent_app_number] => 12/985289
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/985289 | Static random access memory with data controlled power supply | Jan 4, 2011 | Issued |
Array
(
[id] => 8726922
[patent_doc_number] => 08406058
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[patent_issue_date] => 2013-03-26
[patent_title] => 'Read only memory and operating method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/983985 | Read only memory and operating method thereof | Jan 3, 2011 | Issued |
Array
(
[id] => 8207714
[patent_doc_number] => 20120127813
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[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'DEVICE AND METHOD FOR STORING ERROR INFORMATION OF MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/982705
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[pdf_file] => publications/A1/0127/20120127813.pdf
[firstpage_image] =>[orig_patent_app_number] => 12982705
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/982705 | Device and method for storing error information of memory | Dec 29, 2010 | Issued |
Array
(
[id] => 8714674
[patent_doc_number] => 08400817
[patent_country] => US
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[patent_issue_date] => 2013-03-19
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/979039
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/979039 | Semiconductor device | Dec 26, 2010 | Issued |
Array
(
[id] => 8739734
[patent_doc_number] => 08411513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-02
[patent_title] => 'Techniques for providing a semiconductor memory device having hierarchical bit lines'
[patent_app_type] => utility
[patent_app_number] => 12/974939
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/974939 | Techniques for providing a semiconductor memory device having hierarchical bit lines | Dec 20, 2010 | Issued |
Array
(
[id] => 7536496
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[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/971723
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[pdf_file] => patents/08/050/08050135.pdf
[firstpage_image] =>[orig_patent_app_number] => 12971723
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/971723 | Semiconductor memory device | Dec 16, 2010 | Issued |
Array
(
[id] => 8739722
[patent_doc_number] => 08411502
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[patent_kind] => B2
[patent_issue_date] => 2013-04-02
[patent_title] => 'Flash memory device using adaptive program verification scheme and related method of operation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/963867 | Flash memory device using adaptive program verification scheme and related method of operation | Dec 8, 2010 | Issued |
Array
(
[id] => 8573202
[patent_doc_number] => 08339855
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[patent_title] => 'Reverse order page writing in flash memories'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/961431 | Reverse order page writing in flash memories | Dec 5, 2010 | Issued |
Array
(
[id] => 8226346
[patent_doc_number] => 20120140551
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[patent_title] => 'STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/959883 | Static random access memory (SRAM) write assist circuit with leakage suppression and level control | Dec 2, 2010 | Issued |
Array
(
[id] => 8376691
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[patent_title] => 'Method of reading dual-bit memory cell'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/914020 | Method of reading dual-bit memory cell | Oct 27, 2010 | Issued |
Array
(
[id] => 8677012
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[patent_title] => 'Memory circuit and method of operating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/913087 | Memory circuit and method of operating the same | Oct 26, 2010 | Issued |
Array
(
[id] => 8284237
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[patent_title] => 'Stacked memory device having a scalable bandwidth interface'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/902599 | Stacked memory device having a scalable bandwidth interface | Oct 11, 2010 | Issued |
12/895094 | SEMICONDUCTOR MEMORY DEVICE AND MODULE FOR HIGH FREQUENCY OPERATION | Sep 29, 2010 | Abandoned |
Array
(
[id] => 8544861
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/882685 | Nonvolatile semiconductor memory device | Sep 14, 2010 | Issued |
Array
(
[id] => 6093207
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[patent_title] => 'RESISTANCE CHANGE TYPE MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/881919 | RESISTANCE CHANGE TYPE MEMORY | Sep 13, 2010 | Abandoned |
Array
(
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[patent_title] => 'LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/876703 | Latency counter, semiconductor memory device including the same, and data processing system | Sep 6, 2010 | Issued |