Christopher M. Roland

Array ( [id] => 16959183 [patent_doc_number] => 11063066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => C-axis alignment of an oxide film over an oxide semiconductor film [patent_app_type] => utility [patent_app_number] => 16/420858 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 72 [patent_no_of_words] => 32434 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14875779 [patent_doc_number] => 20190288131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SUBSTRATES HAVING AN ANTIREFLECTION LAYER AND METHODS OF FORMING AN ANTIREFLECTION LAYER [patent_app_type] => utility [patent_app_number] => 16/383747 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16383747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17652925 [patent_doc_number] => 11355667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice [patent_app_type] => utility [patent_app_number] => 16/380091 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4940 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15835699 [patent_doc_number] => 20200133132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHOD FOR REMOVING PHOTORESISTOR LAYER, METHOD OF FORMING A PATTERN AND METHOD OF MANUFACTURING A PACKAGE [patent_app_type] => utility [patent_app_number] => 16/379821 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18402308 [patent_doc_number] => 11664459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Method for making an inverted T channel field effect transistor (ITFET) including a superlattice [patent_app_type] => utility [patent_app_number] => 16/380142 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4731 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17221211 [patent_doc_number] => 11173697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate [patent_app_type] => utility [patent_app_number] => 16/379117 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8544 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17410180 [patent_doc_number] => 11251077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Method of forming a semiconductor device with air gaps for low capacitance interconnects [patent_app_type] => utility [patent_app_number] => 16/379402 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3038 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16364469 [patent_doc_number] => 20200321220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => LAYER-BY-LAYER ETCHING OF POLY-GRANULAR METAL-BASED MATERIALS FOR SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/378072 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15030645 [patent_doc_number] => 20190326327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => DEVICE SUBSTRATE, DISPLAY PANEL AND TILED DISPLAY [patent_app_type] => utility [patent_app_number] => 16/373597 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16373597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18205692 [patent_doc_number] => 11588101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Hall sensor with performance control [patent_app_type] => utility [patent_app_number] => 16/370944 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6989 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16348402 [patent_doc_number] => 20200313053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => HIGH POWER LED ASSEMBLY AND METHOD OF FORMING A HIGH POWER LED ASSEMBLY [patent_app_type] => utility [patent_app_number] => 16/370936 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304590 [patent_doc_number] => 11626507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration [patent_app_type] => utility [patent_app_number] => 16/370722 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 58 [patent_no_of_words] => 10185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304590 [patent_doc_number] => 11626507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration [patent_app_type] => utility [patent_app_number] => 16/370722 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 58 [patent_no_of_words] => 10185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14938795 [patent_doc_number] => 20190305036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => MICRO LED SEMI-FINISHED PRODUCT MODULE [patent_app_type] => utility [patent_app_number] => 16/370749 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16928315 [patent_doc_number] => 11049806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Semiconductor device including semiconductor chip transmitting signals at high speed [patent_app_type] => utility [patent_app_number] => 16/370370 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 19879 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 595 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14938281 [patent_doc_number] => 20190304779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => MANUFACTURING METHOD OF CRYSTALLIZED METAL OXIDE LAYER, MANUFACTURING METHOD OF ACTIVE DEVICE SUBSTRATE, AND ACTIVE DEVICE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/368891 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304590 [patent_doc_number] => 11626507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration [patent_app_type] => utility [patent_app_number] => 16/370722 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 58 [patent_no_of_words] => 10185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14938599 [patent_doc_number] => 20190304938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SYSTEMS AND METHODS FOR WAFER-LEVEL MANUFACTURING OF DEVICES HAVING LAND GRID ARRAY INTERFACES [patent_app_type] => utility [patent_app_number] => 16/369967 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17607331 [patent_doc_number] => 11335823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Silicon carbide ultraviolet light photodetector [patent_app_type] => utility [patent_app_number] => 16/370636 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304590 [patent_doc_number] => 11626507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration [patent_app_type] => utility [patent_app_number] => 16/370722 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 58 [patent_no_of_words] => 10185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370722 [rel_patent_id] =>[rel_patent_doc_number] =>)