Search

Christopher M. Roland

Examiner (ID: 753, Phone: (571)270-1271 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2814, 2893
Total Applications
637
Issued Applications
382
Pending Applications
66
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18016617 [patent_doc_number] => 11508925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Photovoltaic device [patent_app_type] => utility [patent_app_number] => 15/746575 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15746575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/746575
Photovoltaic device Jul 17, 2016 Issued
Array ( [id] => 11118171 [patent_doc_number] => 20160315145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN AND CIRCUIT FORMED' [patent_app_type] => utility [patent_app_number] => 15/201130 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201130
Circuit structure having islands between source and drain and circuit formed Jun 30, 2016 Issued
Array ( [id] => 13043543 [patent_doc_number] => 10043914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Semiconductor device comprising a plurality of oxide semiconductor layers [patent_app_type] => utility [patent_app_number] => 15/175183 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 69 [patent_no_of_words] => 19782 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175183
Semiconductor device comprising a plurality of oxide semiconductor layers Jun 6, 2016 Issued
Array ( [id] => 12027107 [patent_doc_number] => 20170317207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'TRENCH MOSFET STRUCTURE AND LAYOUT WITH SEPARATED SHIELDED GATE' [patent_app_type] => utility [patent_app_number] => 15/141907 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 4385 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141907
TRENCH MOSFET STRUCTURE AND LAYOUT WITH SEPARATED SHIELDED GATE Apr 28, 2016 Abandoned
Array ( [id] => 11227521 [patent_doc_number] => 09455247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'High-performance device for protection from electrostatic discharge' [patent_app_type] => utility [patent_app_number] => 15/087622 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087622 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087622
High-performance device for protection from electrostatic discharge Mar 30, 2016 Issued
Array ( [id] => 13799415 [patent_doc_number] => 20190013246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION [patent_app_type] => utility [patent_app_number] => 16/068095 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16068095 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/068095
ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION Mar 27, 2016 Abandoned
Array ( [id] => 11972550 [patent_doc_number] => 20170276704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'OPTICAL DEVICE PACKAGE AND OPTICAL SWITCH' [patent_app_type] => utility [patent_app_number] => 15/508988 [patent_app_country] => US [patent_app_date] => 2016-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5803 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/508988
OPTICAL DEVICE PACKAGE AND OPTICAL SWITCH Mar 21, 2016 Abandoned
Array ( [id] => 11972550 [patent_doc_number] => 20170276704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'OPTICAL DEVICE PACKAGE AND OPTICAL SWITCH' [patent_app_type] => utility [patent_app_number] => 15/508988 [patent_app_country] => US [patent_app_date] => 2016-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5803 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/508988
OPTICAL DEVICE PACKAGE AND OPTICAL SWITCH Mar 21, 2016 Abandoned
Array ( [id] => 13799631 [patent_doc_number] => 20190013354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => DAMASCENE-BASED APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/067803 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067803
Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures Mar 17, 2016 Issued
Array ( [id] => 17745791 [patent_doc_number] => 11393873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures [patent_app_type] => utility [patent_app_number] => 16/067800 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10061 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067800
Approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures Mar 6, 2016 Issued
Array ( [id] => 13799629 [patent_doc_number] => 20190013353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/067801 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067801 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067801
APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES Mar 6, 2016 Abandoned
Array ( [id] => 10984565 [patent_doc_number] => 20160181510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/056376 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2817 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/056376
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Feb 28, 2016 Abandoned
Array ( [id] => 16944212 [patent_doc_number] => 11056463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Arrangement of penetrating electrode interconnections [patent_app_type] => utility [patent_app_number] => 15/528883 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 27435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/528883
Arrangement of penetrating electrode interconnections Dec 10, 2015 Issued
Array ( [id] => 12061849 [patent_doc_number] => 20170338193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'POWER SEMICONDUCTOR MODULE WITH SHORT-CIRCUIT FAILURE MODE' [patent_app_type] => utility [patent_app_number] => 15/520872 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520872 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520872
POWER SEMICONDUCTOR MODULE WITH SHORT-CIRCUIT FAILURE MODE Oct 13, 2015 Abandoned
Array ( [id] => 10753097 [patent_doc_number] => 20160099249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR' [patent_app_type] => utility [patent_app_number] => 14/874392 [patent_app_country] => US [patent_app_date] => 2015-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7165 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14874392 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/874392
Method of forming integrated fin and strap structure for an access transistor of a trench capacitor Oct 2, 2015 Issued
Array ( [id] => 13321039 [patent_doc_number] => 20180212057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => DEEP EPI ENABLED BY BACKSIDE REVEAL FOR STRESS ENHANCEMENT & CONTACT [patent_app_type] => utility [patent_app_number] => 15/747111 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15747111 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/747111
Deep EPI enabled by backside reveal for stress enhancement and contact Sep 24, 2015 Issued
Array ( [id] => 10666987 [patent_doc_number] => 20160013132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'SEMICONDUCTOR WIRING PATTERNS' [patent_app_type] => utility [patent_app_number] => 14/863756 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9232 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863756 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/863756
Semiconductor wiring patterns Sep 23, 2015 Issued
Array ( [id] => 14801367 [patent_doc_number] => 10403694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => OLED substrate comprising corresponding pixel definition layer patterns, manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 15/124444 [patent_app_country] => US [patent_app_date] => 2015-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4795 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15124444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/124444
OLED substrate comprising corresponding pixel definition layer patterns, manufacturing method thereof, and display device Jul 29, 2015 Issued
Array ( [id] => 13683005 [patent_doc_number] => 20160380239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => METHOD FOR MANUFACTURING AMOLED DISPLAY DEVICE AND STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 14/777741 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14777741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/777741
METHOD FOR MANUFACTURING AMOLED DISPLAY DEVICE AND STRUCTURE THEREOF Jul 22, 2015 Abandoned
Array ( [id] => 15015495 [patent_doc_number] => 10453908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Organic light emitting diode display comprising interlayer insulating layers [patent_app_type] => utility [patent_app_number] => 14/794167 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794167
Organic light emitting diode display comprising interlayer insulating layers Jul 7, 2015 Issued
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