
Christopher M. Roland
Examiner (ID: 7129, Phone: (571)270-1271 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2893, 2814 |
| Total Applications | 621 |
| Issued Applications | 375 |
| Pending Applications | 60 |
| Abandoned Applications | 204 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19524068
[patent_doc_number] => 12125808
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Method for protecting data stored in a memory, and corresponding integrated circuit
[patent_app_type] => utility
[patent_app_number] => 18/206923
[patent_app_country] => US
[patent_app_date] => 2023-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5563
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206923
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/206923 | Method for protecting data stored in a memory, and corresponding integrated circuit | Jun 6, 2023 | Issued |
Array
(
[id] => 18661285
[patent_doc_number] => 20230307298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION
[patent_app_type] => utility
[patent_app_number] => 18/205456
[patent_app_country] => US
[patent_app_date] => 2023-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9830
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205456
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/205456 | ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION | Jun 1, 2023 | Pending |
Array
(
[id] => 20268719
[patent_doc_number] => 12439734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-07
[patent_title] => Semiconductor device comprising electron blocking layer
[patent_app_type] => utility
[patent_app_number] => 18/144000
[patent_app_country] => US
[patent_app_date] => 2023-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 1145
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144000
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/144000 | Semiconductor device comprising electron blocking layer | May 4, 2023 | Issued |
Array
(
[id] => 18586184
[patent_doc_number] => 20230268449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => PHOTOSENSITIVE TRANSISTOR, METHOD FOR MANUFACTURING A PHOTOSENSITIVE TRANSISTOR, AND MICROFLUIDIC CHIP
[patent_app_type] => utility
[patent_app_number] => 18/142114
[patent_app_country] => US
[patent_app_date] => 2023-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11486
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142114
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/142114 | PHOTOSENSITIVE TRANSISTOR, METHOD FOR MANUFACTURING A PHOTOSENSITIVE TRANSISTOR, AND MICROFLUIDIC CHIP | May 1, 2023 | Pending |
Array
(
[id] => 18540911
[patent_doc_number] => 20230246022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => ELECTRONIC COMPONENT, ELECTRONIC CIRCUIT, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT
[patent_app_type] => utility
[patent_app_number] => 18/160914
[patent_app_country] => US
[patent_app_date] => 2023-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12498
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160914
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/160914 | ELECTRONIC COMPONENT, ELECTRONIC CIRCUIT, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT | Jan 26, 2023 | Pending |
Array
(
[id] => 18396944
[patent_doc_number] => 20230165165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => HALL SENSOR WITH PERFORMANCE CONTROL
[patent_app_type] => utility
[patent_app_number] => 18/094631
[patent_app_country] => US
[patent_app_date] => 2023-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7011
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094631
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/094631 | HALL SENSOR WITH PERFORMANCE CONTROL | Jan 8, 2023 | Pending |
Array
(
[id] => 18396944
[patent_doc_number] => 20230165165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => HALL SENSOR WITH PERFORMANCE CONTROL
[patent_app_type] => utility
[patent_app_number] => 18/094631
[patent_app_country] => US
[patent_app_date] => 2023-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7011
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094631
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/094631 | HALL SENSOR WITH PERFORMANCE CONTROL | Jan 8, 2023 | Pending |
Array
(
[id] => 18362930
[patent_doc_number] => 20230144521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => SEMICONDUCTOR DEVICE COMPRISING ELECTRON BLOCKING LAYER
[patent_app_type] => utility
[patent_app_number] => 18/094185
[patent_app_country] => US
[patent_app_date] => 2023-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7300
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094185
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/094185 | Semiconductor device comprising electron blocking layer | Jan 5, 2023 | Issued |
Array
(
[id] => 18874915
[patent_doc_number] => 11862740
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Illuminance sensor, electronic machine and 2D image sensor
[patent_app_type] => utility
[patent_app_number] => 18/066823
[patent_app_country] => US
[patent_app_date] => 2022-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 25663
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066823
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/066823 | Illuminance sensor, electronic machine and 2D image sensor | Dec 14, 2022 | Issued |
Array
(
[id] => 19185320
[patent_doc_number] => 11991939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-21
[patent_title] => Method of manufacturing a memory device comprising introducing a dopant into silicon oxide
[patent_app_type] => utility
[patent_app_number] => 18/079161
[patent_app_country] => US
[patent_app_date] => 2022-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 26
[patent_no_of_words] => 8344
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079161
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/079161 | Method of manufacturing a memory device comprising introducing a dopant into silicon oxide | Dec 11, 2022 | Issued |
Array
(
[id] => 18500689
[patent_doc_number] => 20230223485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-13
[patent_title] => PHOTOVOLTAIC JUNCTIONS AND METHODS OF PRODUCTION
[patent_app_type] => utility
[patent_app_number] => 18/074665
[patent_app_country] => US
[patent_app_date] => 2022-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18074665
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/074665 | Methods of producing a photovoltaic junction including ligand exchange of quantum dots of a film | Dec 4, 2022 | Issued |
Array
(
[id] => 18254131
[patent_doc_number] => 20230081170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => CMOS COMPATIBLE BIOFET
[patent_app_type] => utility
[patent_app_number] => 18/051107
[patent_app_country] => US
[patent_app_date] => 2022-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9858
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051107
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/051107 | CMOS COMPATIBLE BIOFET | Oct 30, 2022 | Pending |
Array
(
[id] => 19139495
[patent_doc_number] => 11974488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-30
[patent_title] => Touch sensing unit integrated display device including outgassing holes
[patent_app_type] => utility
[patent_app_number] => 17/970497
[patent_app_country] => US
[patent_app_date] => 2022-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 33
[patent_no_of_words] => 13376
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970497
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/970497 | Touch sensing unit integrated display device including outgassing holes | Oct 19, 2022 | Issued |
Array
(
[id] => 18282319
[patent_doc_number] => 20230097791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => RESISTIVE SWITCHING MEMORY DEVICE INCLUDING DUAL ACTIVE LAYER, MANUFACTURING METHOD THEREOF, AND ARRAY INCLUDING SAME
[patent_app_type] => utility
[patent_app_number] => 17/956288
[patent_app_country] => US
[patent_app_date] => 2022-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7495
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956288
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/956288 | RESISTIVE SWITCHING MEMORY DEVICE INCLUDING DUAL ACTIVE LAYER, MANUFACTURING METHOD THEREOF, AND ARRAY INCLUDING SAME | Sep 28, 2022 | Pending |
Array
(
[id] => 18147160
[patent_doc_number] => 20230021017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 17/950212
[patent_app_country] => US
[patent_app_date] => 2022-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950212
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/950212 | Vertical gate all around transistor having dual gate structures | Sep 21, 2022 | Issued |
Array
(
[id] => 18147160
[patent_doc_number] => 20230021017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 17/950212
[patent_app_country] => US
[patent_app_date] => 2022-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950212
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/950212 | Vertical gate all around transistor having dual gate structures | Sep 21, 2022 | Issued |
Array
(
[id] => 18139497
[patent_doc_number] => 20230013333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => Array of Capacitors, Array of Memory Cells, Methods of Forming an Array of Capacitors, and Methods of Forming an Array of Memory Cells
[patent_app_type] => utility
[patent_app_number] => 17/950968
[patent_app_country] => US
[patent_app_date] => 2022-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5399
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950968
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/950968 | Arrays of capacitors and arrays of memory cells | Sep 21, 2022 | Issued |
Array
(
[id] => 18111923
[patent_doc_number] => 20230004803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => RECONFIGURABLE MEMTRANSISTORS, FABRICATING METHODS AND APPLICATIONS OF SAME
[patent_app_type] => utility
[patent_app_number] => 17/939057
[patent_app_country] => US
[patent_app_date] => 2022-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12130
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939057
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/939057 | RECONFIGURABLE MEMTRANSISTORS, FABRICATING METHODS AND APPLICATIONS OF SAME | Sep 6, 2022 | Pending |
Array
(
[id] => 18655214
[patent_doc_number] => 20230301065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PRODUCING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/901077
[patent_app_country] => US
[patent_app_date] => 2022-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6404
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901077
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/901077 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PRODUCING THE SAME | Aug 31, 2022 | Pending |
Array
(
[id] => 18221866
[patent_doc_number] => 20230060860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => RESISTIVE MEMORY DEVICE AND PRODUCTION METHOD
[patent_app_type] => utility
[patent_app_number] => 17/900006
[patent_app_country] => US
[patent_app_date] => 2022-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900006
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/900006 | RESISTIVE MEMORY DEVICE AND PRODUCTION METHOD | Aug 30, 2022 | Pending |