
Christopher O. Onuaku
Examiner (ID: 11271)
| Most Active Art Unit | 2615 |
| Art Unit(s) | 2615, 2616, 2712, 2604, 2621, 2715 |
| Total Applications | 508 |
| Issued Applications | 436 |
| Pending Applications | 23 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 185155
[patent_doc_number] => 07645629
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Fabricating CMOS image sensor'
[patent_app_type] => utility
[patent_app_number] => 11/841072
[patent_app_country] => US
[patent_app_date] => 2007-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 2580
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/645/07645629.pdf
[firstpage_image] =>[orig_patent_app_number] => 11841072
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/841072 | Fabricating CMOS image sensor | Aug 19, 2007 | Issued |
Array
(
[id] => 83540
[patent_doc_number] => 07741212
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-22
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/839592
[patent_app_country] => US
[patent_app_date] => 2007-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2684
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/741/07741212.pdf
[firstpage_image] =>[orig_patent_app_number] => 11839592
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/839592 | Semiconductor device and method for manufacturing the same | Aug 15, 2007 | Issued |
Array
(
[id] => 4952679
[patent_doc_number] => 20080185703
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/670543
[patent_app_country] => US
[patent_app_date] => 2007-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2705
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20080185703.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670543
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670543 | Injection molded soldering process and arrangement for three-dimensional structures | Feb 1, 2007 | Issued |
Array
(
[id] => 267098
[patent_doc_number] => 07566623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/670833
[patent_app_country] => US
[patent_app_date] => 2007-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 7089
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/566/07566623.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670833
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670833 | Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device | Feb 1, 2007 | Issued |
Array
(
[id] => 8233290
[patent_doc_number] => 08198735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-12
[patent_title] => 'Integrated circuit package with molded cavity'
[patent_app_type] => utility
[patent_app_number] => 11/670714
[patent_app_country] => US
[patent_app_date] => 2007-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 6391
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/198/08198735.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670714
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670714 | Integrated circuit package with molded cavity | Feb 1, 2007 | Issued |
Array
(
[id] => 359688
[patent_doc_number] => 07485567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Microelectronic circuit structure with layered low dielectric constant regions and method of forming same'
[patent_app_type] => utility
[patent_app_number] => 11/670524
[patent_app_country] => US
[patent_app_date] => 2007-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3746
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/485/07485567.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670524
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670524 | Microelectronic circuit structure with layered low dielectric constant regions and method of forming same | Feb 1, 2007 | Issued |
Array
(
[id] => 4952631
[patent_doc_number] => 20080185655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'SMICONDUCTOR DEVICE, METHOD FOR FABRICATING THEREOF AND METHOD FOR INCREASING FILM STRESS'
[patent_app_type] => utility
[patent_app_number] => 11/670584
[patent_app_country] => US
[patent_app_date] => 2007-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3755
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20080185655.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670584
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670584 | SMICONDUCTOR DEVICE, METHOD FOR FABRICATING THEREOF AND METHOD FOR INCREASING FILM STRESS | Feb 1, 2007 | Abandoned |
Array
(
[id] => 4669922
[patent_doc_number] => 20080044982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL FOR A DISPLAY DEVICE AND A METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/627683
[patent_app_country] => US
[patent_app_date] => 2007-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 8189
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20080044982.pdf
[firstpage_image] =>[orig_patent_app_number] => 11627683
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/627683 | THIN FILM TRANSISTOR ARRAY PANEL FOR A DISPLAY DEVICE AND A METHOD OF MANUFACTURING THE SAME | Jan 25, 2007 | Abandoned |
Array
(
[id] => 256747
[patent_doc_number] => 07576425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Conducting layer in chip package module'
[patent_app_type] => utility
[patent_app_number] => 11/657734
[patent_app_country] => US
[patent_app_date] => 2007-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1860
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/576/07576425.pdf
[firstpage_image] =>[orig_patent_app_number] => 11657734
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/657734 | Conducting layer in chip package module | Jan 24, 2007 | Issued |
Array
(
[id] => 4876771
[patent_doc_number] => 20080150154
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'METHOD FOR FABRICATING A CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/623581
[patent_app_country] => US
[patent_app_date] => 2007-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 7055
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20080150154.pdf
[firstpage_image] =>[orig_patent_app_number] => 11623581
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/623581 | METHOD FOR FABRICATING A CIRCUIT | Jan 15, 2007 | Abandoned |
Array
(
[id] => 587375
[patent_doc_number] => 07439172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-21
[patent_title] => 'Circuit structure with low dielectric constant regions and method of forming same'
[patent_app_type] => utility
[patent_app_number] => 11/623478
[patent_app_country] => US
[patent_app_date] => 2007-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3476
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/439/07439172.pdf
[firstpage_image] =>[orig_patent_app_number] => 11623478
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/623478 | Circuit structure with low dielectric constant regions and method of forming same | Jan 15, 2007 | Issued |
Array
(
[id] => 52863
[patent_doc_number] => 07772031
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-10
[patent_title] => 'Semiconductor apparatus manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/650495
[patent_app_country] => US
[patent_app_date] => 2007-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5600
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/772/07772031.pdf
[firstpage_image] =>[orig_patent_app_number] => 11650495
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/650495 | Semiconductor apparatus manufacturing method | Jan 7, 2007 | Issued |
Array
(
[id] => 5046097
[patent_doc_number] => 20070264770
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'CAPACITOR FORMING METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/618796
[patent_app_country] => US
[patent_app_date] => 2006-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3538
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20070264770.pdf
[firstpage_image] =>[orig_patent_app_number] => 11618796
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618796 | CAPACITOR FORMING METHOD | Dec 29, 2006 | Abandoned |
Array
(
[id] => 4933017
[patent_doc_number] => 20080003792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Method for forming a gate of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/647865
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0003/20080003792.pdf
[firstpage_image] =>[orig_patent_app_number] => 11647865
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/647865 | Method for forming a gate of a semiconductor device | Dec 28, 2006 | Abandoned |
Array
(
[id] => 5219820
[patent_doc_number] => 20070161131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'Measurement method for low-k material'
[patent_app_type] => utility
[patent_app_number] => 11/646094
[patent_app_country] => US
[patent_app_date] => 2006-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0161/20070161131.pdf
[firstpage_image] =>[orig_patent_app_number] => 11646094
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/646094 | Measurement method for low-k material | Dec 25, 2006 | Abandoned |
Array
(
[id] => 4985995
[patent_doc_number] => 20070152333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-05
[patent_title] => 'Metal Interconnection of Semiconductor Device and Method of Fabricating the Same'
[patent_app_type] => utility
[patent_app_number] => 11/616044
[patent_app_country] => US
[patent_app_date] => 2006-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0152/20070152333.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616044
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616044 | Metal Interconnection of Semiconductor Device and Method of Fabricating the Same | Dec 25, 2006 | Abandoned |
Array
(
[id] => 211467
[patent_doc_number] => 07622373
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Memory device having implanted oxide to block electron drift, and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/615563
[patent_app_country] => US
[patent_app_date] => 2006-12-22
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/07/622/07622373.pdf
[firstpage_image] =>[orig_patent_app_number] => 11615563
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615563 | Memory device having implanted oxide to block electron drift, and method of manufacturing the same | Dec 21, 2006 | Issued |
Array
(
[id] => 5188677
[patent_doc_number] => 20070166985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Fabrication Method of Thin Film and Metal Line in Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 11/614101
[patent_app_country] => US
[patent_app_date] => 2006-12-21
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[pdf_file] => publications/A1/0166/20070166985.pdf
[firstpage_image] =>[orig_patent_app_number] => 11614101
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614101 | Fabrication Method of Thin Film and Metal Line in Semiconductor Device | Dec 20, 2006 | Abandoned |
Array
(
[id] => 4648822
[patent_doc_number] => 20080036077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'Package structure and heat sink module thereof'
[patent_app_type] => utility
[patent_app_number] => 11/642552
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0036/20080036077.pdf
[firstpage_image] =>[orig_patent_app_number] => 11642552
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/642552 | Package structure and heat sink module thereof | Dec 20, 2006 | Abandoned |
Array
(
[id] => 836933
[patent_doc_number] => 07393748
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-01
[patent_title] => 'Method of fabricating a semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/609614
[patent_app_country] => US
[patent_app_date] => 2006-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/393/07393748.pdf
[firstpage_image] =>[orig_patent_app_number] => 11609614
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/609614 | Method of fabricating a semiconductor memory device | Dec 11, 2006 | Issued |