
Christopher O. Onuaku
Examiner (ID: 11271)
| Most Active Art Unit | 2615 |
| Art Unit(s) | 2615, 2616, 2712, 2604, 2621, 2715 |
| Total Applications | 508 |
| Issued Applications | 436 |
| Pending Applications | 23 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5019564
[patent_doc_number] => 20070145530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/635813
[patent_app_country] => US
[patent_app_date] => 2006-12-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0145/20070145530.pdf
[firstpage_image] =>[orig_patent_app_number] => 11635813
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/635813 | Semiconductor device and method of manufacturing the same | Dec 7, 2006 | Issued |
Array
(
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[patent_doc_number] => 20080135988
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[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'Method to reduce semiconductor device leakage'
[patent_app_type] => utility
[patent_app_number] => 11/636144
[patent_app_country] => US
[patent_app_date] => 2006-12-07
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11636144
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/636144 | Method to reduce semiconductor device leakage | Dec 6, 2006 | Abandoned |
Array
(
[id] => 4785654
[patent_doc_number] => 20080138983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'Method of forming tensile stress films for NFET performance enhancement'
[patent_app_type] => utility
[patent_app_number] => 11/634303
[patent_app_country] => US
[patent_app_date] => 2006-12-06
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11634303
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/634303 | Method of forming tensile stress films for NFET performance enhancement | Dec 5, 2006 | Abandoned |
Array
(
[id] => 5168821
[patent_doc_number] => 20070069252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-29
[patent_title] => 'Insulated gate semiconductor device having a clamping element to clamp gate-emitter voltage and method of manufacturing thereof'
[patent_app_type] => utility
[patent_app_number] => 11/604717
[patent_app_country] => US
[patent_app_date] => 2006-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3289
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/604717 | Insulated gate semiconductor device having a clamping element to clamp gate-emitter voltage and method of manufacturing thereof | Nov 27, 2006 | Abandoned |
Array
(
[id] => 4899426
[patent_doc_number] => 20080119040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-22
[patent_title] => 'Method for forming a dual damascene structure'
[patent_app_type] => utility
[patent_app_number] => 11/602344
[patent_app_country] => US
[patent_app_date] => 2006-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 11602344
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/602344 | Method for forming a dual damascene structure | Nov 20, 2006 | Abandoned |
Array
(
[id] => 602425
[patent_doc_number] => 07432188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-07
[patent_title] => 'Structure of bumps forming on an under metallurgy layer and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 11/601684
[patent_app_country] => US
[patent_app_date] => 2006-11-20
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[pdf_file] => patents/07/432/07432188.pdf
[firstpage_image] =>[orig_patent_app_number] => 11601684
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/601684 | Structure of bumps forming on an under metallurgy layer and method for making the same | Nov 19, 2006 | Issued |
Array
(
[id] => 5095709
[patent_doc_number] => 20070117318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'Method of manufacturing NAND flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/593914
[patent_app_country] => US
[patent_app_date] => 2006-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1489
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[pdf_file] => publications/A1/0117/20070117318.pdf
[firstpage_image] =>[orig_patent_app_number] => 11593914
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/593914 | Method of manufacturing NAND flash memory device | Nov 6, 2006 | Abandoned |
Array
(
[id] => 4476958
[patent_doc_number] => 07906401
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-03-15
[patent_title] => 'Method of tuning threshold voltages of interdiffusible structures'
[patent_app_type] => utility
[patent_app_number] => 11/602444
[patent_app_country] => US
[patent_app_date] => 2006-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2968
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[pdf_file] => patents/07/906/07906401.pdf
[firstpage_image] =>[orig_patent_app_number] => 11602444
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/602444 | Method of tuning threshold voltages of interdiffusible structures | Oct 31, 2006 | Issued |
Array
(
[id] => 4988728
[patent_doc_number] => 20070155067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-05
[patent_title] => 'METHOD OF FABRICATING POLYCRYSTALLINE SILICON FILM AND METHOD OF FABRICATING THIN FILM TRANSISTOR USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/553693
[patent_app_country] => US
[patent_app_date] => 2006-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0155/20070155067.pdf
[firstpage_image] =>[orig_patent_app_number] => 11553693
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/553693 | METHOD OF FABRICATING POLYCRYSTALLINE SILICON FILM AND METHOD OF FABRICATING THIN FILM TRANSISTOR USING THE SAME | Oct 26, 2006 | Abandoned |
Array
(
[id] => 797939
[patent_doc_number] => 07427525
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-23
[patent_title] => 'Methods for coupling diamond structures to photonic devices'
[patent_app_type] => utility
[patent_app_number] => 11/580344
[patent_app_country] => US
[patent_app_date] => 2006-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[pdf_file] => patents/07/427/07427525.pdf
[firstpage_image] =>[orig_patent_app_number] => 11580344
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/580344 | Methods for coupling diamond structures to photonic devices | Oct 12, 2006 | Issued |
Array
(
[id] => 349221
[patent_doc_number] => 07495339
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-24
[patent_title] => 'Connection structure and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/544633
[patent_app_country] => US
[patent_app_date] => 2006-10-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/544633 | Connection structure and method for fabricating the same | Oct 9, 2006 | Issued |
Array
(
[id] => 5159930
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[patent_issue_date] => 2007-07-26
[patent_title] => 'Fabrication method of CMOS image sensor'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/544754 | Fabrication method of CMOS image sensor | Oct 9, 2006 | Abandoned |
Array
(
[id] => 4980661
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[patent_title] => 'Mounting board and semiconductor device'
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Array
(
[id] => 849101
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[patent_title] => 'Gate etch process for a high-voltage FET'
[patent_app_type] => utility
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Array
(
[id] => 5136063
[patent_doc_number] => 20070077692
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[patent_issue_date] => 2007-04-05
[patent_title] => 'Liquid crystal display device and fabricating method thereof'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/529434 | Liquid crystal display device and fabricating method thereof | Sep 28, 2006 | Issued |
Array
(
[id] => 4941788
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[patent_title] => 'SEMICONDUCTOR DEVICES CONTAINING NITRIDED HIGH DIELECTRIC CONSTANT FILMS'
[patent_app_type] => utility
[patent_app_number] => 11/537492
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/537492 | SEMICONDUCTOR DEVICES CONTAINING NITRIDED HIGH DIELECTRIC CONSTANT FILMS | Sep 28, 2006 | Abandoned |
Array
(
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[patent_issue_date] => 2009-02-24
[patent_title] => 'Methods for uniform doping of non-planar transistor structures'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/540074 | Method of providing solder bumps on a substrate using localized heating | Sep 27, 2006 | Issued |
Array
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[patent_title] => 'THIN FILM TRANSISTOR, ORGANIC ELECTRO-LUMINESCENT DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309735 | Method of fabricating thin film transistor and organic electro-luminescent display device | Sep 18, 2006 | Issued |