Search

Christopher O. Onuaku

Examiner (ID: 11271)

Most Active Art Unit
2615
Art Unit(s)
2615, 2616, 2712, 2604, 2621, 2715
Total Applications
508
Issued Applications
436
Pending Applications
23
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 178290 [patent_doc_number] => 07655999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'High density photodiodes' [patent_app_type] => utility [patent_app_number] => 11/532191 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 11698 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/655/07655999.pdf [firstpage_image] =>[orig_patent_app_number] => 11532191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532191
High density photodiodes Sep 14, 2006 Issued
Array ( [id] => 4701769 [patent_doc_number] => 20080061291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/517571 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8591 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061291.pdf [firstpage_image] =>[orig_patent_app_number] => 11517571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517571
Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method Sep 7, 2006 Issued
Array ( [id] => 4667232 [patent_doc_number] => 20080042292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'BOND PAD FOR WAFER AND PACKAGE FOR CMOS IMAGER' [patent_app_type] => utility [patent_app_number] => 11/465622 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3511 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20080042292.pdf [firstpage_image] =>[orig_patent_app_number] => 11465622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465622
Bond pad for wafer and package for CMOS imager Aug 17, 2006 Issued
Array ( [id] => 5066705 [patent_doc_number] => 20070187806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Semiconductor chip package mounting structure implementing flexible circuit board' [patent_app_type] => utility [patent_app_number] => 11/505323 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3878 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187806.pdf [firstpage_image] =>[orig_patent_app_number] => 11505323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/505323
Semiconductor chip package mounting structure implementing flexible circuit board Aug 16, 2006 Abandoned
Array ( [id] => 4667097 [patent_doc_number] => 20080042157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'SURFACE MOUNT LIGHT EMITTING DIODE PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/464832 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1910 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20080042157.pdf [firstpage_image] =>[orig_patent_app_number] => 11464832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464832
SURFACE MOUNT LIGHT EMITTING DIODE PACKAGE Aug 15, 2006 Abandoned
Array ( [id] => 4667209 [patent_doc_number] => 20080042269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'BUMP STRUCTURES AND PACKAGED STRUCTURES THEREOF' [patent_app_type] => utility [patent_app_number] => 11/465042 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4984 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20080042269.pdf [firstpage_image] =>[orig_patent_app_number] => 11465042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465042
BUMP STRUCTURES AND PACKAGED STRUCTURES THEREOF Aug 15, 2006 Abandoned
Array ( [id] => 871971 [patent_doc_number] => 07361521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Method of manufacturing vertical GaN-based light emitting diode' [patent_app_type] => utility [patent_app_number] => 11/503944 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2665 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/361/07361521.pdf [firstpage_image] =>[orig_patent_app_number] => 11503944 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/503944
Method of manufacturing vertical GaN-based light emitting diode Aug 14, 2006 Issued
Array ( [id] => 4997653 [patent_doc_number] => 20070040287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Method for forming capacitor in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/504274 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3426 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040287.pdf [firstpage_image] =>[orig_patent_app_number] => 11504274 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504274
Method for forming capacitor in a semiconductor device Aug 14, 2006 Abandoned
Array ( [id] => 4688265 [patent_doc_number] => 20080032446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => ' COMBINATION HEAT DISSIPATION DEVICE WITH TERMINATION AND A METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/462662 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4693 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032446.pdf [firstpage_image] =>[orig_patent_app_number] => 11462662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462662
COMBINATION HEAT DISSIPATION DEVICE WITH TERMINATION AND A METHOD OF MAKING THE SAME Aug 3, 2006 Abandoned
Array ( [id] => 4685594 [patent_doc_number] => 20080029775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Light emitting diode package with positioning groove' [patent_app_type] => utility [patent_app_number] => 11/497412 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4795 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029775.pdf [firstpage_image] =>[orig_patent_app_number] => 11497412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497412
Light emitting diode package with positioning groove Aug 1, 2006 Abandoned
Array ( [id] => 4692838 [patent_doc_number] => 20080085609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'METHOD FOR PROTECTING HIGH-TOPOGRAPHY REGIONS DURING PATTERNING OF LOW-TOPOGRAPHY REGIONS' [patent_app_type] => utility [patent_app_number] => 11/461033 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085609.pdf [firstpage_image] =>[orig_patent_app_number] => 11461033 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461033
METHOD FOR PROTECTING HIGH-TOPOGRAPHY REGIONS DURING PATTERNING OF LOW-TOPOGRAPHY REGIONS Jul 30, 2006 Abandoned
Array ( [id] => 5038135 [patent_doc_number] => 20070090417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/495662 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090417.pdf [firstpage_image] =>[orig_patent_app_number] => 11495662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495662
Semiconductor device and method for fabricating the same Jul 30, 2006 Abandoned
Array ( [id] => 5205150 [patent_doc_number] => 20070026632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method of manufacturing a semiconductor device and the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/492823 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16066 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026632.pdf [firstpage_image] =>[orig_patent_app_number] => 11492823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492823
Method of manufacturing a semiconductor device and the semiconductor device Jul 25, 2006 Issued
Array ( [id] => 891965 [patent_doc_number] => 07344959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-18 [patent_title] => 'Metal filled through via structure for providing vertical wafer-to-wafer interconnection' [patent_app_type] => utility [patent_app_number] => 11/459784 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5763 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344959.pdf [firstpage_image] =>[orig_patent_app_number] => 11459784 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459784
Metal filled through via structure for providing vertical wafer-to-wafer interconnection Jul 24, 2006 Issued
Array ( [id] => 5732914 [patent_doc_number] => 20060258031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Wafer-level electro-optical semiconductor manufacture fabrication method' [patent_app_type] => utility [patent_app_number] => 11/488764 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2185 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258031.pdf [firstpage_image] =>[orig_patent_app_number] => 11488764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/488764
Wafer-level electro-optical semiconductor manufacture fabrication method Jul 18, 2006 Abandoned
Array ( [id] => 228776 [patent_doc_number] => 07601589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Method of manufacturing flash memory device' [patent_app_type] => utility [patent_app_number] => 11/454594 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3719 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/601/07601589.pdf [firstpage_image] =>[orig_patent_app_number] => 11454594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/454594
Method of manufacturing flash memory device Jun 15, 2006 Issued
Array ( [id] => 4691211 [patent_doc_number] => 20080083981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Thermally Enhanced BGA Packages and Methods' [patent_app_type] => utility [patent_app_number] => 11/422863 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3759 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083981.pdf [firstpage_image] =>[orig_patent_app_number] => 11422863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422863
Thermally Enhanced BGA Packages and Methods Jun 6, 2006 Abandoned
Array ( [id] => 5242302 [patent_doc_number] => 20070020797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Self-aligned process for manufacturing phase change memory cells' [patent_app_type] => utility [patent_app_number] => 11/445924 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5259 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020797.pdf [firstpage_image] =>[orig_patent_app_number] => 11445924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/445924
Self-aligned process for manufacturing phase change memory cells Jun 1, 2006 Issued
Array ( [id] => 4803108 [patent_doc_number] => 20080014696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Trench capacitor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/444324 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1521 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014696.pdf [firstpage_image] =>[orig_patent_app_number] => 11444324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444324
Trench capacitor and method of manufacturing the same May 31, 2006 Abandoned
Array ( [id] => 5049114 [patent_doc_number] => 20070029658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Electrical connection pattern in an electronic panel' [patent_app_type] => utility [patent_app_number] => 11/445966 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2683 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20070029658.pdf [firstpage_image] =>[orig_patent_app_number] => 11445966 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/445966
Electrical connection pattern in an electronic panel May 31, 2006 Issued
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