Search

Christopher P. Ellis

Examiner (ID: 2055, Phone: (571)272-6914 , Office: P/3644 )

Most Active Art Unit
3644
Art Unit(s)
3651, 2899, 3106, 3644, 3618, 3105, 3611, 2816
Total Applications
2508
Issued Applications
2183
Pending Applications
146
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19865960 [patent_doc_number] => 20250104746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/829789 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829789
MEMORY AND OPERATING METHOD THEREOF Sep 9, 2024 Pending
Array ( [id] => 20396704 [patent_doc_number] => 20250372179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY SYSTEMS, OPERATION METHODS THEREOF, AND COMPUTER READABLE STORAGE MEDIA [patent_app_type] => utility [patent_app_number] => 18/822074 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18822074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/822074
MEMORY SYSTEMS, OPERATION METHODS THEREOF, AND COMPUTER READABLE STORAGE MEDIA Aug 29, 2024 Pending
Array ( [id] => 19803731 [patent_doc_number] => 20250069656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => NON-VOLATILE MEMORY DEVICE, CORRESPONDING METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/813662 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813662
NON-VOLATILE MEMORY DEVICE, CORRESPONDING METHOD AND SYSTEM Aug 22, 2024 Pending
Array ( [id] => 19604453 [patent_doc_number] => 20240395333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => FLOATING DATA LINE CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/790595 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790595
FLOATING DATA LINE CIRCUIT AND METHOD Jul 30, 2024 Pending
Array ( [id] => 19589366 [patent_doc_number] => 20240386923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => CONTENT ADDRESSABLE MEMORY FOR LARGE SEARCH WORDS [patent_app_type] => utility [patent_app_number] => 18/789540 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789540
CONTENT ADDRESSABLE MEMORY FOR LARGE SEARCH WORDS Jul 29, 2024 Pending
Array ( [id] => 19589422 [patent_doc_number] => 20240386979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => Bit Selection for Power Reduction in Stacking Structure During Memory Programming [patent_app_type] => utility [patent_app_number] => 18/786718 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786718
Bit Selection for Power Reduction in Stacking Structure During Memory Programming Jul 28, 2024 Pending
Array ( [id] => 19618886 [patent_doc_number] => 20240404566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL [patent_app_type] => utility [patent_app_number] => 18/783924 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783924
HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL Jul 24, 2024 Pending
Array ( [id] => 19711128 [patent_doc_number] => 20250021270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => INTERFACE CIRCUIT FOR CONVERTING A SERIAL DATA STREAM TO A PARALLEL DATA SCHEME WITH DATA STROBE PREAMBLE INFORMATION IN THE SERIAL DATA STREAM [patent_app_type] => utility [patent_app_number] => 18/779269 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779269 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779269
INTERFACE CIRCUIT FOR CONVERTING A SERIAL DATA STREAM TO A PARALLEL DATA SCHEME WITH DATA STROBE PREAMBLE INFORMATION IN THE SERIAL DATA STREAM Jul 21, 2024 Pending
Array ( [id] => 19726919 [patent_doc_number] => 20250029670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => METHODS OF OPERATING MAGNETIC MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/774226 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774226
METHODS OF OPERATING MAGNETIC MEMORY DEVICES Jul 15, 2024 Pending
Array ( [id] => 19820732 [patent_doc_number] => 20250078939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => ENHANCED COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/771819 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771819
ENHANCED COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE Jul 11, 2024 Pending
Array ( [id] => 19696091 [patent_doc_number] => 20250014636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/763776 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763776
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT Jul 2, 2024 Pending
Array ( [id] => 20203919 [patent_doc_number] => 12406702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Switches to reduce routing rails of memory system [patent_app_type] => utility [patent_app_number] => 18/763048 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763048 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763048
Switches to reduce routing rails of memory system Jul 2, 2024 Issued
Array ( [id] => 20088558 [patent_doc_number] => 20250218494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => Staggered Write Control for Dual-Interlocked Cells [patent_app_type] => utility [patent_app_number] => 18/761171 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761171 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761171
Staggered Write Control for Dual-Interlocked Cells Jun 30, 2024 Pending
Array ( [id] => 19574856 [patent_doc_number] => 20240379148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Time-Varying Threshold for Usage-Based Disturbance Mitigation [patent_app_type] => utility [patent_app_number] => 18/659305 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659305
Time-Varying Threshold for Usage-Based Disturbance Mitigation May 8, 2024 Pending
Array ( [id] => 19420768 [patent_doc_number] => 20240296892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MEMORY BLOCK CHARACTERISTIC DETERMINATION [patent_app_type] => utility [patent_app_number] => 18/659845 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659845
Memory block characteristic determination May 8, 2024 Issued
Array ( [id] => 20161138 [patent_doc_number] => 12387771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory device for supporting new command input scheme and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/654443 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654443
Memory device for supporting new command input scheme and method of operating the same May 2, 2024 Issued
Array ( [id] => 20274662 [patent_doc_number] => 12444446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Dynamic sensing levels for nonvolatile memory devices [patent_app_type] => utility [patent_app_number] => 18/642283 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642283
Dynamic sensing levels for nonvolatile memory devices Apr 21, 2024 Issued
Array ( [id] => 20071856 [patent_doc_number] => 20250210078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SYSTEM AND METHOD FOR IMPROVING EFFICIENCY OF MULTI-STORAGE-ROW COMPUTE-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 18/642339 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642339
SYSTEM AND METHOD FOR IMPROVING EFFICIENCY OF MULTI-STORAGE-ROW COMPUTE-IN-MEMORY Apr 21, 2024 Pending
Array ( [id] => 19363931 [patent_doc_number] => 20240265965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => PRE-DECODER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/639690 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639690
Pre-decoder circuitry Apr 17, 2024 Issued
Array ( [id] => 19481843 [patent_doc_number] => 20240329885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/634610 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634610
Signal development caching in a memory device Apr 11, 2024 Issued
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