Search

Christopher P. Grey

Examiner (ID: 9751, Phone: (571)272-3160 , Office: P/2413 )

Most Active Art Unit
2413
Art Unit(s)
2667, 2411, OPA, 2615, 2413, 2474, 2616, 2416
Total Applications
643
Issued Applications
454
Pending Applications
23
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16624595 [patent_doc_number] => 20210043248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => ROW HAMMER PREVENTION CIRCUIT, A MEMORY MODULE INCLUDING THE ROW HAMMER PREVENTION CIRCUIT, AND A MEMORY SYSTEM INCLUDING THE MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 16/858468 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16858468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/858468
Row hammer prevention circuit, a memory module including the row hammer prevention circuit, and a memory system including the memory module Apr 23, 2020 Issued
Array ( [id] => 17606922 [patent_doc_number] => 11335414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Method of determining read reference voltage for blocks based on number of erroneous bits [patent_app_type] => utility [patent_app_number] => 16/858256 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7127 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16858256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/858256
Method of determining read reference voltage for blocks based on number of erroneous bits Apr 23, 2020 Issued
Array ( [id] => 16781871 [patent_doc_number] => 20210118950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => 3T2R BINARY WEIGHT CELL WITH HIGH ON/OFF FOR MEMORY DEVICE PROGRAMMED WITH TRANSVERSE CURRENTS [patent_app_type] => utility [patent_app_number] => 16/850691 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/850691
System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs) Apr 15, 2020 Issued
Array ( [id] => 16394210 [patent_doc_number] => 20200335151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => LOW-POWER MEMORY [patent_app_type] => utility [patent_app_number] => 16/849616 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849616 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849616
LOW-POWER MEMORY Apr 14, 2020 Abandoned
Array ( [id] => 17158789 [patent_doc_number] => 20210319840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => IMPEDANCE CALIBRATION VIA A NUMBER OF CALIBRATION CIRCUITS, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/848093 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848093 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848093
Impedance calibration via a number of calibration circuits, and associated methods, devices, and systems Apr 13, 2020 Issued
Array ( [id] => 17158776 [patent_doc_number] => 20210319827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => SEMICONDUCTOR DEVICE PROTECTION CIRCUITS FOR PROTECTING A SEMICONDUCTOR DEVICE DURING PROCESSING THEROF, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/846120 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846120
Semiconductor device protection circuits for protecting a semiconductor device during processing thereof, and associated methods, devices, and systems Apr 9, 2020 Issued
Array ( [id] => 16943940 [patent_doc_number] => 11056188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Three dimensional nonvolatile memory device including channel structure and resistance change memory layer [patent_app_type] => utility [patent_app_number] => 16/844662 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10417 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844662
Three dimensional nonvolatile memory device including channel structure and resistance change memory layer Apr 8, 2020 Issued
Array ( [id] => 17787579 [patent_doc_number] => 11410713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Apparatuses and methods for detecting illegal commands and command sequences [patent_app_type] => utility [patent_app_number] => 16/840946 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7965 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840946
Apparatuses and methods for detecting illegal commands and command sequences Apr 5, 2020 Issued
Array ( [id] => 18248808 [patent_doc_number] => 11605404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Power circuit that interrupts supply of power to a volatile memory in response to a signal indicating a malfunction of a processor [patent_app_type] => utility [patent_app_number] => 16/840178 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2065 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840178
Power circuit that interrupts supply of power to a volatile memory in response to a signal indicating a malfunction of a processor Apr 2, 2020 Issued
Array ( [id] => 17469985 [patent_doc_number] => 11276467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Method of programming memory device and related memory device having a channel-stacked structure [patent_app_type] => utility [patent_app_number] => 16/836885 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5875 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836885
Method of programming memory device and related memory device having a channel-stacked structure Mar 30, 2020 Issued
Array ( [id] => 17558903 [patent_doc_number] => 11315622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => DDR5 four-phase generator with improved metastability resistance [patent_app_type] => utility [patent_app_number] => 16/834144 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834144 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834144
DDR5 four-phase generator with improved metastability resistance Mar 29, 2020 Issued
Array ( [id] => 16193896 [patent_doc_number] => 20200234745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => DUAL RAIL MEMORY, MEMORY MACRO AND ASSOCIATED HYBRID POWER SUPPLY METHOD [patent_app_type] => utility [patent_app_number] => 16/833033 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833033
Dual rail memory, memory macro and associated hybrid power supply method Mar 26, 2020 Issued
Array ( [id] => 17825841 [patent_doc_number] => 11430796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => SRAM layout scheme for improving write margin [patent_app_type] => utility [patent_app_number] => 16/830983 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830983
SRAM layout scheme for improving write margin Mar 25, 2020 Issued
Array ( [id] => 16723521 [patent_doc_number] => 20210090668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Flash Device Endurance Test Method [patent_app_type] => utility [patent_app_number] => 16/830740 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830740
Erase-write cycling method of a flash device Mar 25, 2020 Issued
Array ( [id] => 16379079 [patent_doc_number] => 20200327921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY READING METHOD [patent_app_type] => utility [patent_app_number] => 16/828545 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828545
Non-volatile memory read method for improving read margin Mar 23, 2020 Issued
Array ( [id] => 16928063 [patent_doc_number] => 11049552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-29 [patent_title] => Write assist circuitry for memory [patent_app_type] => utility [patent_app_number] => 16/827959 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827959
Write assist circuitry for memory Mar 23, 2020 Issued
Array ( [id] => 17288933 [patent_doc_number] => 11205490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Method of improving read current stability in analog non-volatile memory cells by screening memory cells [patent_app_type] => utility [patent_app_number] => 16/828206 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828206
Method of improving read current stability in analog non-volatile memory cells by screening memory cells Mar 23, 2020 Issued
Array ( [id] => 16987785 [patent_doc_number] => 11074964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation [patent_app_type] => utility [patent_app_number] => 16/825041 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7316 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825041
Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation Mar 19, 2020 Issued
Array ( [id] => 16677043 [patent_doc_number] => 20210065809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/821225 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821225
Semiconductor devices having increased efficiency in generation of gate-induced drain leakage current without insulation deterioration and methods of operating the same Mar 16, 2020 Issued
Array ( [id] => 17002361 [patent_doc_number] => 11081183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Memory system and control method of memory system for controlling of first and second writing operations [patent_app_type] => utility [patent_app_number] => 16/815073 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10028 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/815073
Memory system and control method of memory system for controlling of first and second writing operations Mar 10, 2020 Issued
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