Search

Christopher P. Schwartz

Examiner (ID: 18793, Phone: (571)272-7123 , Office: P/3657 )

Most Active Art Unit
3657
Art Unit(s)
3657, 3616, 3683, 3613, 3103
Total Applications
4234
Issued Applications
3574
Pending Applications
202
Abandoned Applications
496

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1549615 [patent_doc_number] => 06374340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of managing memory for a PCI bus' [patent_app_type] => B1 [patent_app_number] => 09/497561 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4028 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374340.pdf [firstpage_image] =>[orig_patent_app_number] => 09497561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497561
Method of managing memory for a PCI bus Apr 13, 2000 Issued
09/544853 CACHE PARTIAL WRITE FOR CACHE CONTROL METHOD AND APPARATUS Apr 5, 2000 Abandoned
Array ( [id] => 1425144 [patent_doc_number] => 06535950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Semiconductor memory device having a refresh operation' [patent_app_type] => B1 [patent_app_number] => 09/536988 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 121 [patent_no_of_words] => 18515 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535950.pdf [firstpage_image] =>[orig_patent_app_number] => 09536988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536988
Semiconductor memory device having a refresh operation Mar 28, 2000 Issued
Array ( [id] => 1552869 [patent_doc_number] => 06446168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity' [patent_app_type] => B1 [patent_app_number] => 09/532995 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5145 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446168.pdf [firstpage_image] =>[orig_patent_app_number] => 09532995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532995
Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity Mar 21, 2000 Issued
Array ( [id] => 1540553 [patent_doc_number] => 06490656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Retaining state information of an array of elements by subdividing the array into groups of elements' [patent_app_type] => B1 [patent_app_number] => 09/507324 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2064 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490656.pdf [firstpage_image] =>[orig_patent_app_number] => 09507324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507324
Retaining state information of an array of elements by subdividing the array into groups of elements Feb 17, 2000 Issued
Array ( [id] => 1495368 [patent_doc_number] => 06418522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Translation lookaside buffer for virtual memory systems' [patent_app_type] => B1 [patent_app_number] => 09/501741 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3801 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418522.pdf [firstpage_image] =>[orig_patent_app_number] => 09501741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501741
Translation lookaside buffer for virtual memory systems Feb 10, 2000 Issued
Array ( [id] => 1462403 [patent_doc_number] => 06427188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method and system for early tag accesses for lower-level caches in parallel with first-level cache' [patent_app_type] => B1 [patent_app_number] => 09/501396 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427188.pdf [firstpage_image] =>[orig_patent_app_number] => 09501396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501396
Method and system for early tag accesses for lower-level caches in parallel with first-level cache Feb 8, 2000 Issued
Array ( [id] => 7645911 [patent_doc_number] => 06477612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Providing access to physical memory allocated to a process by selectively mapping pages of the physical memory with virtual memory allocated to the process' [patent_app_type] => B1 [patent_app_number] => 09/499918 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8940 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477612.pdf [firstpage_image] =>[orig_patent_app_number] => 09499918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499918
Providing access to physical memory allocated to a process by selectively mapping pages of the physical memory with virtual memory allocated to the process Feb 7, 2000 Issued
Array ( [id] => 1525137 [patent_doc_number] => 06353332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Methods for implementing CAM functions using dual-port RAM' [patent_app_type] => B1 [patent_app_number] => 09/499498 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 12065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353332.pdf [firstpage_image] =>[orig_patent_app_number] => 09499498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499498
Methods for implementing CAM functions using dual-port RAM Feb 6, 2000 Issued
Array ( [id] => 1592372 [patent_doc_number] => 06360310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Apparatus and method for instruction cache access' [patent_app_type] => B1 [patent_app_number] => 09/496786 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4592 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360310.pdf [firstpage_image] =>[orig_patent_app_number] => 09496786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496786
Apparatus and method for instruction cache access Feb 2, 2000 Issued
09/496876 System and method for effectively utilizing a cache memory in an electronic device Feb 1, 2000 Abandoned
Array ( [id] => 1567284 [patent_doc_number] => 06438641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Information processing apparatus using index and tag addresses for cache access' [patent_app_type] => B1 [patent_app_number] => 09/495954 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7208 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438641.pdf [firstpage_image] =>[orig_patent_app_number] => 09495954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495954
Information processing apparatus using index and tag addresses for cache access Feb 1, 2000 Issued
Array ( [id] => 7642391 [patent_doc_number] => 06430655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Scratchpad RAM memory accessible in parallel to a primary cache' [patent_app_type] => B1 [patent_app_number] => 09/494488 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4796 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430655.pdf [firstpage_image] =>[orig_patent_app_number] => 09494488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494488
Scratchpad RAM memory accessible in parallel to a primary cache Jan 30, 2000 Issued
Array ( [id] => 1602268 [patent_doc_number] => 06493809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Maintaining order of write operations in a multiprocessor for memory consistency' [patent_app_type] => B1 [patent_app_number] => 09/493782 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7473 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493809.pdf [firstpage_image] =>[orig_patent_app_number] => 09493782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493782
Maintaining order of write operations in a multiprocessor for memory consistency Jan 27, 2000 Issued
Array ( [id] => 1466187 [patent_doc_number] => 06393522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method and apparatus for cache memory management' [patent_app_type] => B1 [patent_app_number] => 09/493043 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2850 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393522.pdf [firstpage_image] =>[orig_patent_app_number] => 09493043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493043
Method and apparatus for cache memory management Jan 26, 2000 Issued
Array ( [id] => 1471919 [patent_doc_number] => 06460113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'System and method for performing backup operations using a fibre channel fabric in a multi-computer environment' [patent_app_type] => B1 [patent_app_number] => 09/491578 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2842 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460113.pdf [firstpage_image] =>[orig_patent_app_number] => 09491578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491578
System and method for performing backup operations using a fibre channel fabric in a multi-computer environment Jan 24, 2000 Issued
Array ( [id] => 1241549 [patent_doc_number] => 06683372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Memory expansion module with stacked memory packages and a serial storage unit' [patent_app_type] => B1 [patent_app_number] => 09/442850 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3569 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683372.pdf [firstpage_image] =>[orig_patent_app_number] => 09442850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442850
Memory expansion module with stacked memory packages and a serial storage unit Nov 17, 1999 Issued
Array ( [id] => 1474896 [patent_doc_number] => 06408359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Storage device management system and method for distributively storing data in a plurality of storage devices' [patent_app_type] => B1 [patent_app_number] => 09/435369 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16678 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408359.pdf [firstpage_image] =>[orig_patent_app_number] => 09435369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435369
Storage device management system and method for distributively storing data in a plurality of storage devices Nov 7, 1999 Issued
Array ( [id] => 4350680 [patent_doc_number] => 06334165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Address type determination for an I2C EEPROM' [patent_app_type] => 1 [patent_app_number] => 9/436107 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334165.pdf [firstpage_image] =>[orig_patent_app_number] => 436107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436107
Address type determination for an I2C EEPROM Nov 7, 1999 Issued
Array ( [id] => 1024806 [patent_doc_number] => 06889284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method and apparatus for supporting SDRAM memory' [patent_app_type] => utility [patent_app_number] => 09/420887 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4177 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889284.pdf [firstpage_image] =>[orig_patent_app_number] => 09420887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420887
Method and apparatus for supporting SDRAM memory Oct 18, 1999 Issued
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