Search

Christopher Robin Tate

Examiner (ID: 8775, Phone: (571)272-0970 , Office: P/1655 )

Most Active Art Unit
1655
Art Unit(s)
1808, 1654, 1649, 1655, 1621, 1651
Total Applications
1779
Issued Applications
1014
Pending Applications
276
Abandoned Applications
495

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19662839 [patent_doc_number] => 20240429904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => ASYNCRONOUS RESETTING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/826526 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826526 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826526
ASYNCRONOUS RESETTING INTEGRATED CIRCUITS Sep 5, 2024 Pending
Array ( [id] => 20572975 [patent_doc_number] => 20260066904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => RESETTABLE LEVEL SHIFTING LATCH [patent_app_type] => utility [patent_app_number] => 18/821349 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821349
Resettable level shifting latch Aug 29, 2024 Issued
Array ( [id] => 20124985 [patent_doc_number] => 20250240016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/822068 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18822068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/822068
SEMICONDUCTOR APPARATUS Aug 29, 2024 Pending
Array ( [id] => 20483084 [patent_doc_number] => 12531561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Phase-locked loop control circuit, phase-locked loop circuit and control method thereof [patent_app_type] => utility [patent_app_number] => 18/817238 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817238
Phase-locked loop control circuit, phase-locked loop circuit and control method thereof Aug 27, 2024 Issued
Array ( [id] => 19605673 [patent_doc_number] => 20240396553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => LEVEL SHIFTING CIRCUIT MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/790551 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790551
Level shifting circuit manufacturing method Jul 30, 2024 Issued
Array ( [id] => 19590739 [patent_doc_number] => 20240388296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals [patent_app_type] => utility [patent_app_number] => 18/786702 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786702
Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals Jul 28, 2024 Issued
Array ( [id] => 19750183 [patent_doc_number] => 20250038748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => LEVEL SHIFTER ENABLE [patent_app_type] => utility [patent_app_number] => 18/773324 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773324 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773324
Level shifter enable Jul 14, 2024 Issued
Array ( [id] => 20204547 [patent_doc_number] => 12407337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Flip-flop circuit and method [patent_app_type] => utility [patent_app_number] => 18/768843 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768843 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768843
Flip-flop circuit and method Jul 9, 2024 Issued
Array ( [id] => 19547305 [patent_doc_number] => 20240364341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals [patent_app_type] => utility [patent_app_number] => 18/767158 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767158
Semiconductor device including a level shifter and method of mitigating a delay between input and output signals Jul 8, 2024 Issued
Array ( [id] => 20176399 [patent_doc_number] => 12395159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Leakage-free dummy cell for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/764205 [patent_app_country] => US [patent_app_date] => 2024-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764205
Leakage-free dummy cell for semiconductor devices Jul 3, 2024 Issued
Array ( [id] => 20430218 [patent_doc_number] => 20250392311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => VOLTAGE LEVEL DOWN-SHIFTING CIRCUIT STRUCTURE WITH INPUT STAGE PULL-DOWN CAPACITOR [patent_app_type] => utility [patent_app_number] => 18/749829 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749829
Voltage level down-shifting circuit structure with input stage pull-down capacitor Jun 20, 2024 Issued
Array ( [id] => 20223610 [patent_doc_number] => 20250286541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => PHASE FREQUENCY DETECTOR AND ITS METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 18/747995 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747995
PHASE FREQUENCY DETECTOR AND ITS METHOD OF OPERATION Jun 18, 2024 Abandoned
Array ( [id] => 20011840 [patent_doc_number] => 20250150062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => LATCH CALIBRATION SYSTEM AND LATCH DRIVING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/746075 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746075 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746075
LATCH CALIBRATION SYSTEM AND LATCH DRIVING SYSTEM Jun 17, 2024 Issued
Array ( [id] => 19647287 [patent_doc_number] => 20240421807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVER DEVICE [patent_app_type] => utility [patent_app_number] => 18/742244 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742244
SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVER DEVICE Jun 12, 2024 Pending
Array ( [id] => 20674520 [patent_doc_number] => 12615047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Input buffer circuit having a signal splitter and combiner circuit [patent_app_type] => utility [patent_app_number] => 18/742762 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1307 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742762
Input buffer circuit having a signal splitter and combiner circuit Jun 12, 2024 Issued
Array ( [id] => 19635377 [patent_doc_number] => 20240413826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => FAST-LOCKING PHASE-LOCKED LOOP, FREQUENCY DIVIDER, AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/738586 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738586
Fast-locking phase-locked loop, frequency divider, and communication device Jun 9, 2024 Issued
Array ( [id] => 19485224 [patent_doc_number] => 20240333266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTEGRATED CIRCUIT HAVING LATCH WITH TRANSISTORS OF DIFFERENT GATE WIDTHS [patent_app_type] => utility [patent_app_number] => 18/676873 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676873
Integrated circuit having latch with transistors of different gate widths May 28, 2024 Issued
Array ( [id] => 19865810 [patent_doc_number] => 20250104596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => GATE DRIVER [patent_app_type] => utility [patent_app_number] => 18/675139 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675139
Gate driver May 27, 2024 Issued
Array ( [id] => 20495634 [patent_doc_number] => 12537516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Single pin clock-free retention flip-flop [patent_app_type] => utility [patent_app_number] => 18/666532 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666532
Single pin clock-free retention flip-flop May 15, 2024 Issued
Array ( [id] => 19393562 [patent_doc_number] => 20240283432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => LOGARITHMIC DEMODULATOR FOR LASER WAVELENGTH-MODULATON SPECTROSCOPY [patent_app_type] => utility [patent_app_number] => 18/644540 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644540
LOGARITHMIC DEMODULATOR FOR LASER WAVELENGTH-MODULATON SPECTROSCOPY Apr 23, 2024 Abandoned
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