
Christopher Veraa
Examiner (ID: 16821, Phone: (571)272-2329 , Office: P/3638 )
| Most Active Art Unit | 3636 |
| Art Unit(s) | 3638, 3611, 3636 |
| Total Applications | 954 |
| Issued Applications | 418 |
| Pending Applications | 29 |
| Abandoned Applications | 518 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 432625
[patent_doc_number] => 07265399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-04
[patent_title] => 'Asymetric layout structures for transistors and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/977227
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[pdf_file] => patents/07/265/07265399.pdf
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Array
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[patent_issue_date] => 2006-05-04
[patent_title] => 'Semiconductor light emitting devices with graded compositon light emitting layers'
[patent_app_type] => utility
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Array
(
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[patent_title] => ' Capacitor structure having hemispherical grains'
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Array
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[patent_issue_date] => 2011-01-11
[patent_title] => 'MBE growth of a semiconductor laser diode'
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Array
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[patent_title] => 'Package structure of multi-chips light-emitting module'
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Array
(
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Array
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[patent_title] => 'Transistor with a strained region and method of manufacture'
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Array
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[id] => 5810751
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[patent_title] => 'Light emitting semiconductor bonding structure and method of manufacturing the same'
[patent_app_type] => utility
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/962367 | MOS-gated transistor with reduced miller capacitance | Oct 7, 2004 | Issued |
Array
(
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[patent_title] => 'Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device'
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Array
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Array
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Array
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Array
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