Search

Christopher Veraa

Examiner (ID: 16821, Phone: (571)272-2329 , Office: P/3638 )

Most Active Art Unit
3636
Art Unit(s)
3638, 3611, 3636
Total Applications
954
Issued Applications
418
Pending Applications
29
Abandoned Applications
518

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 759370 [patent_doc_number] => 07015567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure' [patent_app_type] => utility [patent_app_number] => 10/815407 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015567.pdf [firstpage_image] =>[orig_patent_app_number] => 10815407 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815407
Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure Mar 31, 2004 Issued
Array ( [id] => 7609505 [patent_doc_number] => 06998684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'High mobility plane CMOS SOI' [patent_app_type] => utility [patent_app_number] => 10/708907 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 42 [patent_no_of_words] => 7513 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998684.pdf [firstpage_image] =>[orig_patent_app_number] => 10708907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708907
High mobility plane CMOS SOI Mar 30, 2004 Issued
Array ( [id] => 751736 [patent_doc_number] => 07023037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Integrated circuit devices having dielectric regions protected with multi-layer insulation structures' [patent_app_type] => utility [patent_app_number] => 10/813335 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11027 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023037.pdf [firstpage_image] =>[orig_patent_app_number] => 10813335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813335
Integrated circuit devices having dielectric regions protected with multi-layer insulation structures Mar 29, 2004 Issued
Array ( [id] => 7036767 [patent_doc_number] => 20050156201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/807247 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156201.pdf [firstpage_image] =>[orig_patent_app_number] => 10807247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/807247
Semiconductor device Mar 23, 2004 Issued
Array ( [id] => 691955 [patent_doc_number] => 07075125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Power semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/806397 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6881 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075125.pdf [firstpage_image] =>[orig_patent_app_number] => 10806397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/806397
Power semiconductor device Mar 22, 2004 Issued
Array ( [id] => 6955688 [patent_doc_number] => 20050212058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Resistance-reduced semiconductor device and fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/806217 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2212 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212058.pdf [firstpage_image] =>[orig_patent_app_number] => 10806217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/806217
Resistance-reduced semiconductor device and fabrication thereof Mar 22, 2004 Abandoned
Array ( [id] => 7016458 [patent_doc_number] => 20050218475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Low power fuse structure and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/805747 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1249 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20050218475.pdf [firstpage_image] =>[orig_patent_app_number] => 10805747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805747
Low power fuse structure and method of making the same Mar 21, 2004 Issued
Array ( [id] => 503047 [patent_doc_number] => 07205611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Semiconductor device including a protection circuit' [patent_app_type] => utility [patent_app_number] => 10/805040 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10812 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205611.pdf [firstpage_image] =>[orig_patent_app_number] => 10805040 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805040
Semiconductor device including a protection circuit Mar 17, 2004 Issued
Array ( [id] => 756229 [patent_doc_number] => 07019348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Embedded semiconductor product with dual depth isolation regions' [patent_app_type] => utility [patent_app_number] => 10/789527 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2159 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019348.pdf [firstpage_image] =>[orig_patent_app_number] => 10789527 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/789527
Embedded semiconductor product with dual depth isolation regions Feb 25, 2004 Issued
Array ( [id] => 682990 [patent_doc_number] => 07081641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/786097 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5022 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081641.pdf [firstpage_image] =>[orig_patent_app_number] => 10786097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786097
Semiconductor device and manufacturing method thereof Feb 25, 2004 Issued
Array ( [id] => 944316 [patent_doc_number] => 06967370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Integrated semiconductor circuit having a multiplicity of memory cells' [patent_app_type] => utility [patent_app_number] => 10/785087 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2947 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967370.pdf [firstpage_image] =>[orig_patent_app_number] => 10785087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785087
Integrated semiconductor circuit having a multiplicity of memory cells Feb 24, 2004 Issued
Array ( [id] => 7447656 [patent_doc_number] => 20040164312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Method of fabricating semiconductor device and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/786667 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8337 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164312.pdf [firstpage_image] =>[orig_patent_app_number] => 10786667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786667
Method of fabricating semiconductor device and semiconductor device Feb 24, 2004 Issued
Array ( [id] => 664043 [patent_doc_number] => 07102155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Electrode substrate, thin film transistor, display device and their production' [patent_app_type] => utility [patent_app_number] => 10/786567 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12223 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102155.pdf [firstpage_image] =>[orig_patent_app_number] => 10786567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786567
Electrode substrate, thin film transistor, display device and their production Feb 24, 2004 Issued
Array ( [id] => 7448291 [patent_doc_number] => 20040164378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Method for fabricating an NPN transistor in a BICMOS technology' [patent_app_type] => new [patent_app_number] => 10/785667 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3241 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164378.pdf [firstpage_image] =>[orig_patent_app_number] => 10785667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785667
Method for fabricating an NPN transistor in a BICMOS technology Feb 23, 2004 Issued
Array ( [id] => 7072666 [patent_doc_number] => 20050145932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Vertical channel field effect transistors having insulating layers thereon and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/780067 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6198 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20050145932.pdf [firstpage_image] =>[orig_patent_app_number] => 10780067 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/780067
Vertical channel field effect transistors having insulating layers thereon Feb 16, 2004 Issued
Array ( [id] => 502816 [patent_doc_number] => 07205573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Light-emitting device having a compound substrate' [patent_app_type] => utility [patent_app_number] => 10/708047 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1740 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205573.pdf [firstpage_image] =>[orig_patent_app_number] => 10708047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708047
Light-emitting device having a compound substrate Feb 4, 2004 Issued
Array ( [id] => 623982 [patent_doc_number] => 07138691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Selective nitridation of gate oxides' [patent_app_type] => utility [patent_app_number] => 10/707897 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4603 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138691.pdf [firstpage_image] =>[orig_patent_app_number] => 10707897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707897
Selective nitridation of gate oxides Jan 21, 2004 Issued
Array ( [id] => 7677561 [patent_doc_number] => 20040152265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Method for forming MRAM bit having a bottom sense layer utilizing electroless plating' [patent_app_type] => new [patent_app_number] => 10/761247 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4242 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152265.pdf [firstpage_image] =>[orig_patent_app_number] => 10761247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761247
MRAM memory cell having an electroplated bottom layer Jan 21, 2004 Issued
Array ( [id] => 975954 [patent_doc_number] => 06933571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Thin film transistors, liquid crystal display device and electronic apparatus using the same' [patent_app_type] => utility [patent_app_number] => 10/757452 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9035 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933571.pdf [firstpage_image] =>[orig_patent_app_number] => 10757452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757452
Thin film transistors, liquid crystal display device and electronic apparatus using the same Jan 14, 2004 Issued
Array ( [id] => 7309406 [patent_doc_number] => 20040142582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Thin film structure from LILAC annealing' [patent_app_type] => new [patent_app_number] => 10/755487 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4022 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142582.pdf [firstpage_image] =>[orig_patent_app_number] => 10755487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755487
Thin film structure from LILAC annealing Jan 11, 2004 Issued
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