Christopher Veraa

Array ( [id] => 7375558 [patent_doc_number] => 20040178484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Interposer, interposer package and device assembly employing the same' [patent_app_type] => new [patent_app_number] => 10/388997 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3737 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178484.pdf [firstpage_image] =>[orig_patent_app_number] => 10388997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7143935 [patent_doc_number] => 20040169205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'MULTIPLE-BIT MEMORY LATCH CELL FOR INTEGRATED CIRCUIT GATE ARRAY' [patent_app_type] => new [patent_app_number] => 10/376837 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4049 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20040169205.pdf [firstpage_image] =>[orig_patent_app_number] => 10376837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1254280 [patent_doc_number] => 06670678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Semiconductor device having ESD protective transistor' [patent_app_type] => B2 [patent_app_number] => 10/377477 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670678.pdf [firstpage_image] =>[orig_patent_app_number] => 10377477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7267764 [patent_doc_number] => 20040056282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/370657 [patent_app_country] => US [patent_app_date] => 2003-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 15010 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20040056282.pdf [firstpage_image] =>[orig_patent_app_number] => 10370657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 638331 [patent_doc_number] => 07126200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Integrated circuits with contemporaneously formed array electrodes and logic interconnects' [patent_app_type] => utility [patent_app_number] => 10/369277 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4352 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126200.pdf [firstpage_image] =>[orig_patent_app_number] => 10369277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1266597 [patent_doc_number] => 06661101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/366347 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 7196 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661101.pdf [firstpage_image] =>[orig_patent_app_number] => 10366347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6704351 [patent_doc_number] => 20030151085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/358617 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7209 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151085.pdf [firstpage_image] =>[orig_patent_app_number] => 10358617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1305957 [patent_doc_number] => 06621119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Isolated stack-gate flash cell structure and its contactless flash memory arrays' [patent_app_type] => B1 [patent_app_number] => 10/358507 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 5719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621119.pdf [firstpage_image] =>[orig_patent_app_number] => 10358507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6841139 [patent_doc_number] => 20030146486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/356517 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7536 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20030146486.pdf [firstpage_image] =>[orig_patent_app_number] => 10356517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6803384 [patent_doc_number] => 20030230778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'SOI structure having a SiGe Layer interposed between the silicon and the insulator' [patent_app_type] => new [patent_app_number] => 10/354197 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6437 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20030230778.pdf [firstpage_image] =>[orig_patent_app_number] => 10354197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6849304 [patent_doc_number] => 20030141506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Nitride semiconductor element with a supporting substrate and a method for producing a nitride semiconductor element' [patent_app_type] => new [patent_app_number] => 10/351497 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 31156 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20030141506.pdf [firstpage_image] =>[orig_patent_app_number] => 10351497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1288380 [patent_doc_number] => 06639251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Light emitting element array module and printer head and micro-display using the same' [patent_app_type] => B1 [patent_app_number] => 10/350477 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639251.pdf [firstpage_image] =>[orig_patent_app_number] => 10350477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700100 [patent_doc_number] => 07067839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Tuning circuit with distributed tunnel junction elements and superconductor integrated circuit comprising the tuning circuit' [patent_app_type] => utility [patent_app_number] => 10/348987 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 7344 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067839.pdf [firstpage_image] =>[orig_patent_app_number] => 10348987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6758856 [patent_doc_number] => 20030122217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Fuse structure' [patent_app_type] => new [patent_app_number] => 10/349731 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1652 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20030122217.pdf [firstpage_image] =>[orig_patent_app_number] => 10349731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180072 [patent_doc_number] => 06744067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Wafer-level testing apparatus and method' [patent_app_type] => B1 [patent_app_number] => 10/347027 [patent_app_country] => US [patent_app_date] => 2003-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4670 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744067.pdf [firstpage_image] =>[orig_patent_app_number] => 10347027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6785742 [patent_doc_number] => 20030136981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Solid-state imaging device' [patent_app_type] => new [patent_app_number] => 10/341707 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20030136981.pdf [firstpage_image] =>[orig_patent_app_number] => 10341707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6963887 [patent_doc_number] => 20050230784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'ADHERING LAYERS TO METALS WITH DIELECTRIC ADHESIVE LAYERS' [patent_app_type] => utility [patent_app_number] => 10/341777 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2229 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230784.pdf [firstpage_image] =>[orig_patent_app_number] => 10341777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1276904 [patent_doc_number] => 06649985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Insulated-gate semiconductor device for a rectifier' [patent_app_type] => B1 [patent_app_number] => 10/332927 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2866 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649985.pdf [firstpage_image] =>[orig_patent_app_number] => 10332927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7318806 [patent_doc_number] => 20040135162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Light emitting diode' [patent_app_type] => new [patent_app_number] => 10/340627 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1441 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135162.pdf [firstpage_image] =>[orig_patent_app_number] => 10340627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1044129 [patent_doc_number] => 06867472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by conductive buried channel depth optimization' [patent_app_type] => utility [patent_app_number] => 10/338517 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3880 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867472.pdf [firstpage_image] =>[orig_patent_app_number] => 10338517 [rel_patent_id] =>[rel_patent_doc_number] =>)